amaranth-lang

amaranth

Python2020–2026

amaranth-lang / amaranth

amaranth

A modern hardware definition language and toolchain based on Python

Hardware & Embedded

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10Distinct people

12Mentions

0Explicit recommenders

2.1KGitHub stars

REPOSITORY AT A GLANCE

What to know before exploring

What it is

A modern hardware definition language and toolchain based on Python

GitHub

Where it is used

No documented product use has been verified yet.

What people are saying

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Also in these discussions

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This week on Hacker News

Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 3:56:07 PM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by year12 dated mentions

Observed mentions: 2020-03-13 10:01:31 UTC to 2026-03-30 09:39:07 UTC.

* An incomplete calendar period is marked with an outlined bar. Its count is not directly comparable with a full period.

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

View mention counts and date ranges

UTC ranges include their start and exclude their end. Select a period to filter the source evidence.
Period	Start (UTC)	End (exclusive, UTC)	Mentions	Submissions	Comments
2020	2020-01-01 00:00:00 UTC	2021-01-01 00:00:00 UTC	1	0	1
2021	2021-01-01 00:00:00 UTC	2022-01-01 00:00:00 UTC	7	2	5
2022	2022-01-01 00:00:00 UTC	2023-01-01 00:00:00 UTC	1	0	1
2023	2023-01-01 00:00:00 UTC	2024-01-01 00:00:00 UTC	0	0	0
2024	2024-01-01 00:00:00 UTC	2025-01-01 00:00:00 UTC	0	0	0
2025	2025-01-01 00:00:00 UTC	2026-01-01 00:00:00 UTC	1	0	1
2026 (partial)	2026-01-01 00:00:00 UTC	2027-01-01 00:00:00 UTC	2	0	2

What Hacker News says

12 sources

Joel_Mckay·Mar 30, 2026

There are folks trying to make HDL easier, and vendor neutral. Not sure why people were upset by mentioning the project... https://github.com/amaranth-lang/amaranth While VHDL makes a fun academic toy language, it has always been Verilog in the commercial settings. Both languages can develop hard to trace bugs when the optimizer decides to simply remove things it thinks are unused. =3

In VHDL's Crown Jewel

Joel_Mckay·Mar 30, 2026

Over the years I have run Altera, Lattice, and Xilinx... and almost all reasonably complex projects were always done in Verilog. If I recall Xilinx fully integrated its Synopsys export workflow a few years back, but not sure where that went after the mergers. The Amaranth HDL python project does look fun =3 https://github.com/amaranth-lang/amaranth

In VHDL's Crown Jewel

magicalhippo·Nov 4, 2025

Very nice project. Playing with FPGAs can be difficult, but also a lot of fun. Must say the code was nicely organized and easy to follow. My own code is a bit of a mess in comparison. Did you try out plain Verilog before going with System Verilog? My plan was to move on to generators like nMigen, now called Amaranth[1], and they spit out Verilog IIRC so decided to learn that for debugging. Then life happened and got sidetracked, but been wanting to pick it up again. How was it to program for the Analogue Pocket? I was recently looking at it as just a portable retro gaming device, but if it's easy to double as a fun FPGA platform then that would be great. [1]: https://github.com/amaranth-lang/amaranth

In Show HN: Tamagotchi P1 for FPGAs

snakke·Mar 21, 2022

As an aside, the latest and active development of nMigen has been rebranded a few months ago to Amaranth and can be found here: https://github.com/amaranth-lang/amaranth . In case people googled nMigen and came to the repository that hasn't been updated in two years.

In VRoom A high end RISC-V implementation

olvy0·Oct 22, 2021Submission

nMigen – A refreshed Python toolbox for building complex digital hardware

97 points · Open discussion

exikyut·Oct 21, 2021

Hmm. A followup question: are there any cheats/hacks that would make it possible (if painful) to for example explore the world of USB3, PCIe, or Linux on low-end-ish ARM (eg https://www.thirtythreeforty.net/posts/2019/12/my-business-c..., based on the tiny 533MHz https://linux-sunxi.org/F1C100s), without needing to buy equipment in the mid-4-figure/low-5-figure range, if I were able to substitute a statistically larger-than-average amount of free time (and discipline)? For example, I learned about https://github.com/GlasgowEmbedded/glasgow recently, a bit of a niche kitchen sink that uses https://github.com/nmigen/nmigen/ to lower a domain-specific subset of Python 3 (https://nmigen.info/nmigen/latest/lang.html) into Verilog which then runs on the Glasgow board's iCE40HX8K. The project basically creates a workflow and hardware to use chea

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p FPGAs for rapid iteration. (The README makes the point that the synthesis is sufficiently fast that caching isn't needed.) In certain extremely specific situations where circumstances align perfectly (caveat emptor), devices like this can sometimes present a temporary escape to the inevitable process of acquiring one's first second-hand high-end oscilloscope (fingers-crossed the expensive bits still have a few years left in them). To some extent they may also commoditize the exploration of very high-speed interfaces, which are rapidly becoming a commonplace principal of computers (eg, having 10Gbps everywhere when USB3.1 hits market saturation will be interesting) faster than test and analysis kit can keep up (eg to do proper hardware security analysis work). The Glasgow is perhaps not quite an answer to that entire statement, but maybe represents beginning steps in that sort of direction. So, to reiterate - it's probably an unhelpfully broad question, and I'm still learning about the field so haven't quite got the preciseness I want yet, but I'm curious what gadgetry, techniques, etc would perhaps allow someone to "hack it" and dive into this stuff on a shoestring budget, on the assumption the ride would be a tad bumpier? :)

In Facts every web dev should know before they burn out and turn to painting

edwinbalani·Sep 3, 2021

Worth knowing that are two "nmigen"s nowadays - the one originated in M-Labs and one under a project also called nmigen: https://github.com/nmigen/nmigen It's a fork, made for reasons, but more actively developed. whitequark (long time author/contributor) works on this fork, and no longer the M-Labs version.

In Awesome Lattice FPGA Boards

pbsds·Aug 30, 2021

You could implement your design in nmigen [1], use it to generate either verilog or rtlil, then use yosys (via [2]) to reduce it to an AND and NOT circuit (using the 'aigmap' command), then visualize it with [3] [1]: https://github.com/nmigen/nmigen [2]: https://yowasp.org [3]: https://github.com/nturley/netlistsvg

In Show HN: Pylectronics – Reproduce digital electronics in Python

ekiwi·Jul 5, 2021

Chisel is not HLS. It is a Scala library that lets you generate circuits on an RTL abstraction level. That means that you explicitly define every state element like registers and memories. But you can generate N registers inside a loop (or a map/foreach) instead of only 1 at a time. In HLS the compiler needs to somehow infer your registers and memories. That said, I think one of the problems the google team was struggling with is that in traditional HW development there is design and a separate verification team. The design team bought into Chisel since it would let them generate hardware more quickly, but the verification team just tried to apply their traditional verification methods on the _generated_ Verilog. This is almost like trying to test the assembly that a C++ compiler generates instead of trying to test the C++ program since a

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ll your testing infrastructure is setup for testing assembly code and that is "what we have always been doing". In order to catch verification up to modern Hardware Construction Languages [0] we need more powerful verification libraries that can allow us to build tests that can automatically adapt to the parameters that were supplied to the hardware generator. There are different groups working on this right now. The jury is still out on how to best solver the "verification gap". In case you are interested: - https://github.com/chiselverify/chiselverify - https://github.com/leonardt/fault - https://github.com/ucb-bar/chisel-testers2/ I am probably missing some approaches from the nmigen world that I am not familiar with. You can always write cocotb [1] tests in python, but I am not sure if they can directly interface with nmigen generators to adapt to their parameterization. [0] besides Chisel, there is also https://github.com/nmigen/nmigen and https://github.com/SpinalHDL/SpinalHDL [1] https://github.com/cocotb/cocotb

In Chisel/FIRRTL Hardware Compiler Framework

stefanpie·Jun 22, 2021Submission

nMigen: A refreshed Python toolbox for building complex digital hardware

1 points · Open discussion

ekiwi·Apr 17, 2021

Sounds like nmigen might be a good open source successor to the project that you describe: https://github.com/nmigen/nmigen There are lots of open-source (n)migen components available through the litex framework: https://github.com/enjoy-digital/litex

In Unifying the CUDA Python Ecosystem

ZirconiumX·Mar 13, 2020

Could you please point [6] at https://github.com/nmigen/nmigen which is the new upstream after a hard fork? Additionally, I'd like to clarify that nMigen generates Verilog indirectly; it actually generates RTLIL, which is the intermediate representation of Yosys, and then Yosys turns it into Verilog after some cleanup passes. I'll happily admit to being biased, but nMigen is so much easier for me to work in than Verilog ever was.

In Qnice – An Elegant 16 Bit Processor