chiselwatt

Well the same guy (yes, he is a madman) did another one in Chisel, which is one step removed from Verilog: https://github.com/antonblanchard/chiselwatt I don't spend enough time with FPGAs to even pretend to have an educated opinion on HDLs.

You might be interested in what Anton Blanchard has been up to with the power ISA soft cores, it seems like his work has spanned the bulk of the FPGA toolkits, and I think his latest is taped out for the SKY130 run. His work is also being adapted for an openBMC replacement, which would offer an opportunity to dust off some old Xzibit templates, so thats good. https://github.com/antonblanchard/microwatt https://github.com/antonblanchard/chiselwatt https://www.efabless.com/projects/29 https://gitlab.raptorengineering.com/kestrel-collaboration/k...

I'm one of the Chisel devs. My biased view is that iterative development with Chisel, to the point of functional verification, is going to be faster than in a traditional RTL language primarily because you have a robust unit testing framework for Scala (Scalatest) and a library for testing Chisel hardware, ChiselTest [^1]. Basically, adopting test driven development is zero-cost---most Chisel users are writing tests as they're designing hardware. Note that there are existing options that help bridge this gap for Verilog/VHDL like VUnit [^2] and cocotb [^3]. For libraries, there's multiple levels. The Chisel standard library is providing basic hardware modules, e.g., queues, counters, arbiters, delay pipes, and pseudo-random number generators, as well as common interfaces, e.g., valid and ready/valid. Then there's an IP contributions repo