verilog-6502

why not just load a 6502 soft core into the fpga a 6502 is about 1200 gates i think, which is very roughly 400 4-luts https://github.com/emeb/ulx3s_6502 simulates a 6502 on a lattice ecp5, using yosys, nextpnr, and the well-known (apparently! i'd never heard of it) https://github.com/Arlet/verilog-6502 documented at https://web.archive.org/web/20230604005701/https://c-scape.n... no word on how much of the fpga it uses reproducing the undocumented instructions will be more work but still will probably fit

Gee, good question. I know people replicate them in FPGAs and verilog [1]. Improving on the design can be potentially done through software with verilog. I'm not sure of anyone who has improved on it because people focus on replicating it (it's a really fun chip to play with). Why fewer transistors though? [1]https://github.com/Arlet/verilog-6502