speculation-barrier

On ARM (A64, A32, T32) we get CSDB barrier, but it's a hint instruction instead of going via MSR registers. From whitepaper CSDB is 1101_0101_0000_0011_0010_0010_100_11111 Here some snippets from ARM manuals: HINT instruction: 1101 0101 0000 0011 0010 0010 100 11111 CRm = 0010 op2 = 100 Some encodings described here are not allocated in this revision of the architecture, and behave as NOPs. (This is important) Hints 18 to 23 variant Applies when CRm == 0010 && op2 != 00x. HINT #<imm> Hint is encoded in CRm:op2 pair, existing similar: 0010:000 ESB // Error Synchronization Barrier 0010:001 PSB CSYNC // Profiling Synchronization Barrier Thus in assembler this is written: hint #0x14 Which is a NOP if SOC does not understand this hint. It's being used here: http://lkml.iu.edu/hypermail/linux/kernel/1801.0/04191.html and also here: https://gith

Maybe it's just because this is a more technical update, but the responses from Intel[1] and AMD really seem like night and day to me. This page is for the most part clearly written and only has a minimal amount of BS before getting to the point about: • identifying the problems (without casting aspersions on other vendors or being FUD-y about issues that don't exist) • specifying what _specific_ hardware is vulnerable • info for developers (here's the patches you need if you're building your own kernel, here's a new compiler intrinsic that will be available soon for your applications, here [2] is code to implement the intrinsic yourself if you're not able to update your compiler) • slightly less useful info for end users (update your stuff, which isn't necessarily actionable advice for some of us on Android) • lets us know that future ha