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Cerelog-ESP-EEG
ESP-EEG
C++2026–2026
Cerelog-ESP-EEG / ESP-EEG

ESP-EEG

Cerelog ESP-EEG High-precision 8-channel biosensing board designed for EEG, EMG, ECG, and Brain Computer Interface (BCI) research applications.

2Distinct people
2Mentions
0Explicit recommenders
180GitHub stars
REPOSITORY AT A GLANCE

What to know before exploring

What it is

Cerelog ESP-EEG High-precision 8-channel biosensing board designed for EEG, EMG, ECG, and Brain Computer Interface (BCI) research applications.

GitHub

Where it is used

No documented product use has been verified yet.

What people are saying

No recommendation phrase was found in the indexed comments.

No classified warning is attached to this page. Read the discussions before treating silence as approval.

Also in these discussions

No other repository is repeatedly linked in the same discussions.

This week on Hacker News

Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 5:04:57 PM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by week2 dated mentions

Observed mentions: 2026-01-05 17:46:51 UTC to 2026-05-16 03:03:52 UTC. Weeks start Monday, UTC.

012026-01-05 00:00:00 UTC to 2026-01-12 00:00:00 UTC (exclusive): 1 mentions; 1 submissions, 0 commentsJan 52026-01-12 00:00:00 UTC to 2026-01-19 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2026-01-19 00:00:00 UTC to 2026-01-26 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2026-01-26 00:00:00 UTC to 2026-02-02 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2026-02-02 00:00:00 UTC to 2026-02-09 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2026-02-09 00:00:00 UTC to 2026-02-16 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2026-02-16 00:00:00 UTC to 2026-02-23 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2026-02-23 00:00:00 UTC to 2026-03-02 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2026-03-02 00:00:00 UTC to 2026-03-09 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2026-03-09 00:00:00 UTC to 2026-03-16 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 commentsMar 92026-03-16 00:00:00 UTC to 2026-03-23 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2026-03-23 00:00:00 UTC to 2026-03-30 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2026-03-30 00:00:00 UTC to 2026-04-06 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2026-04-06 00:00:00 UTC to 2026-04-13 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2026-04-13 00:00:00 UTC to 2026-04-20 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2026-04-20 00:00:00 UTC to 2026-04-27 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2026-04-27 00:00:00 UTC to 2026-05-04 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2026-05-04 00:00:00 UTC to 2026-05-11 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2026-05-11 00:00:00 UTC to 2026-05-18 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 commentsMay 11

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

View mention counts and date ranges
UTC ranges include their start and exclude their end. Select a period to filter the source evidence.
PeriodStart (UTC)End (exclusive, UTC)MentionsSubmissionsComments
Jan 52026-01-05 00:00:00 UTC2026-01-12 00:00:00 UTC110
Jan 122026-01-12 00:00:00 UTC2026-01-19 00:00:00 UTC000
Jan 192026-01-19 00:00:00 UTC2026-01-26 00:00:00 UTC000
Jan 262026-01-26 00:00:00 UTC2026-02-02 00:00:00 UTC000
Feb 22026-02-02 00:00:00 UTC2026-02-09 00:00:00 UTC000
Feb 92026-02-09 00:00:00 UTC2026-02-16 00:00:00 UTC000
Feb 162026-02-16 00:00:00 UTC2026-02-23 00:00:00 UTC000
Feb 232026-02-23 00:00:00 UTC2026-03-02 00:00:00 UTC000
Mar 22026-03-02 00:00:00 UTC2026-03-09 00:00:00 UTC000
Mar 92026-03-09 00:00:00 UTC2026-03-16 00:00:00 UTC000
Mar 162026-03-16 00:00:00 UTC2026-03-23 00:00:00 UTC000
Mar 232026-03-23 00:00:00 UTC2026-03-30 00:00:00 UTC000
Mar 302026-03-30 00:00:00 UTC2026-04-06 00:00:00 UTC000
Apr 62026-04-06 00:00:00 UTC2026-04-13 00:00:00 UTC000
Apr 132026-04-13 00:00:00 UTC2026-04-20 00:00:00 UTC000
Apr 202026-04-20 00:00:00 UTC2026-04-27 00:00:00 UTC000
Apr 272026-04-27 00:00:00 UTC2026-05-04 00:00:00 UTC000
May 42026-05-04 00:00:00 UTC2026-05-11 00:00:00 UTC000
May 112026-05-11 00:00:00 UTC2026-05-18 00:00:00 UTC101

What Hacker News says

2 sources

Show HN: Open-Source 8-Ch BCI Board (ESP32 and ADS1299 and OpenBCI GUI)

Hi HN, I recently shared this on r/BCI and wanted to see what the engineering community here thinks. A while back, I got frustrated with the state of accessible BCI hardware. Research gear was wildly unaffordable. So, I spent a ton of time designing a custom board, software and firmware to bridge that gap. I call it the Cerelog ESP-EEG. It is open-source (Firmware + Schematics), and I designed it specifically to fix the signal integrity issues found in most DIY hardware. I believe in sharing the work. You can find the Schematics, Firmware, and Software setup on the GitHub repo: GITHUB LINK: https://github.com/Cerelog-ESP-EEG/ESP-EEG For those who don't want to deal with BGA soldering or sourcing components, I do have assembled units available: https://www.cerelog.com/eeg_researchers.html The major features: Forked/modified OpenBCI GUI Com
Read the rest
patibility as well as Brainflow API, and LSL Compatibility. I know a lot of us rely on the OpenBCI GUI for visualization because it just works. I didn't want to reinvent the wheel, so I ensured this board supports it natively. It works out of the box: I maintain a forked modified version of the GUI that connects to the board via LSL (Lab Streaming Layer). Zero coding required: You can visualize FFTs, Spectrograms, and EMG widgets immediately without writing a single line of Python. The "active bias" (why my signal is cleaner): The TI ADS1299 is the gold standard for EEG, but many dev boards implement it incorrectly. They often leave the Bias feedback loop "open" (passive), which makes them terrible at rejecting 60Hz mains hum. I simply followed the datasheet: I implemented a True Closed-Loop Active Bias (Drive Right Leg). How it works: It measures the common-mode signal, inverts it, and actively drives it back into the body. The result: Cleaner data Tech stack: ADC: TI ADS1299 (24-bit, 8-channel). MCU: ESP32 Chosen to handle high-speed SPI and WiFi/USB streaming Software: BrainFlow support (Python, C++, Java, C#) for those who want to build custom ML pipelines, LSL support, and forked version of OpenBCI GUI support This was a huge project for me. I’m happy to geek out about getting the ESP32 to stream reliably at high sample rates as both the software and firmware for this project proved a lot more challenging than I expected. Let me know what you think! SAFETY NOTE: I strongly recommend running this on a LiPo battery via WiFi. If you must use USB, please use a laptop running on battery power, not plugged into the wall.
54 points · Open discussion

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