Cores-VeeR-EH1

operations in November 2021 with a mission to "make impossible optimizations possible, at scale and in practice". > There are six universities in TILOS: UCSD, MIT, National University, Penn, UT-Austin, and Yale. The institute seeks a new nexus of AI and machine learning, optimization, and use in practice. Figure 4 shows four virtuous cycles envisioned for the institute: 1. mutual advances of AI and optimization provide the foundations; 2. challenges of scale, along with breakthroughs from scaling, bind together foundations and the use domains of chip design, networks and robotics; 3. the cycle of translation and impact brings research and the leading edge of practice closer together; and 4. the cycle of research, education, and broadening participation grows the field and its workforce. The virtues written here are self evident & obvious. Trying to just get good yourself without trying to help advance the field, not participating, not taking advantages of scale of many working together, not participating in open research, the risks of having isolated teams, and not participating in cycles of development: whatever the nvidia or "publicly traded company" worlds think they're doing, they're missing out, and hurting everyone and especially themselves for this oldschool zero-sum competitive thinking. There are plenty of company's releasing the chips too. Google's OpenTitan[2] security chip. WD's Swerv RISC-V core for their driver controller ARM R-series replacement[3]. Open standards if not chips like UCI for chiplets or CXL for interconnect are again examples of literally everyone but NVidia playing well together, trying for better, standardizing a future for participation & healthy competition & growth. Nvidia again and again is the company which simply will not play with others. I challenge you to answer your own question in reverse: are any companies other than Nvidia embarking up AI/ML chipmaking in a closed fashion? There probably are, let's follow & watch them. [1] https://theopenroadproject.org/news/leveling-up-a-trajectory... [2] https://opentitan.org/ [3] https://github.com/chipsalliance/Cores-SweRV

nk we overestimate how effective and easy to use PIM (processing in ram) could be. Where it will really start to shine is when the processor can retire instructions into the PIM, pre-materialize data streams from the PIM, do a scheduled reduction and then push compute bundles back to memory. The computational ram needs to be integrated with cpu, it can't just be an accelerator. Computational disks might be way way easier to implement. We will know how that is going as soon as Western Digital tells us. https://github.com/chipsalliance/Cores-SweRV