chipsalliance

rocket-chip

Scala2017–2025

chipsalliance / rocket-chip

rocket-chip

Rocket Chip Generator

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What it is

Rocket Chip Generator

GitHub

Where it is used

No documented product use was verified in the last source check.

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Also in these discussions

openhwfoundation/cva6 · linked in 2 of the same discussions
ucb-bar/chiseltest · linked in 2 of the same discussions

Mentioned in the same Hacker News threads. That is not proof they are substitutes.

This week on Hacker News

Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 3:56:07 PM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by year18 dated mentions

Observed mentions: 2017-06-27 08:22:56 UTC to 2025-10-29 15:40:56 UTC.

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

View mention counts and date ranges

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Period	Start (UTC)	End (exclusive, UTC)	Mentions	Comments
2017	2017-01-01 00:00:00 UTC	2018-01-01 00:00:00 UTC	4	4
2018	2018-01-01 00:00:00 UTC	2019-01-01 00:00:00 UTC	4	4
2019	2019-01-01 00:00:00 UTC	2020-01-01 00:00:00 UTC	4	4
2020	2020-01-01 00:00:00 UTC	2021-01-01 00:00:00 UTC	3	3
2021	2021-01-01 00:00:00 UTC	2022-01-01 00:00:00 UTC	0	0
2022	2022-01-01 00:00:00 UTC	2023-01-01 00:00:00 UTC	1	1
2023	2023-01-01 00:00:00 UTC	2024-01-01 00:00:00 UTC	1	1
2024	2024-01-01 00:00:00 UTC	2025-01-01 00:00:00 UTC	0	0
2025	2025-01-01 00:00:00 UTC	2026-01-01 00:00:00 UTC	1	1

What Hacker News says

18 sources

rwmj·Oct 29, 2025

Rocket-chip is widely used (https://github.com/chipsalliance/rocket-chip). It can fit on smaller FPGAs. If you want something very tiny and completely understandable, and don't mind that it's 32 bit, then PicoRV32 (https://github.com/YosysHQ/picorv32).

In Berkeley Out-of-Order RISC-V Processor (Boom) (2020)

rapiz·Mar 26, 2023

It's actually chisel. But github marks it as scala because chisel is based on scala. Other HDL based on scala includes SpinalHDL. These two HDL are pretty welcomed because of opensource and usability. You can find lots of projects in them. Notably rocket-chip, which is also in chisel. https://github.com/chipsalliance/rocket-chip They're around for a while but still young and some people are pushing for adoption.

In Open-source high-performance RISC-V processor

rjsw·Dec 23, 2022

You could do a trial build of an in-order Rocket RISC-V core [1] to see how much space it takes up. [1] https://github.com/chipsalliance/rocket-chip

In RISC-V Pushes into the Mainstream

orbifold·Oct 5, 2020

All the major toolchains work on Linux. I personally liked Pynq http://www.pynq.io/, it works fairly well and is beefy enough to do non-toy projects with it. For something totally barebones you can try https://www.latticesemi.com/Products/DevelopmentBoardsAndKit..., it has the advantage that it has a very nice open source tool flow available for it: http://www.clifford.at/icestorm/. I own both boards and I work professionally with EDA tools, honestly the biggest cliff is setting up tooling and processes around a given project. If you don't want to do everything from scratch you need to either rely on proprietary libraries, which will cost you a fortune and/or lock you into a very specific tool flow (Synopsis Designware libraries). The other alternative is to use one of the open source ecosystems like https://github.com/m-labs/migen or too

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ling around Chisel or various scattered libraries of open-source components which are often hard to get to work together, but also this requires a massive amount of time investment to just get the synthesis / simulation flow working. The situation is slowly improving and there are various university research groups and corporations that have released larger amounts of open source code that one can use as a starting point: - https://github.com/openhwgroup/cva6 (mostly done by ETHZ people initially, also see https://github.com/pulp-platform/pulpino) - https://github.com/chipsalliance/Cores-SweRV-EL2 (one of several high quality open-source RISC-V cores by Western Digital) - https://github.com/chipsalliance/rocket-chip (UCB by initial creators of RISC-V) - https://github.com/electronicvisions/nux (POWER based embedded processor, that we have used in several neuromorphic chip tapeouts (silicon proven)) On the tooling side one great thing that happened is that the verilator open source simulator has gained a lot of traction. - https://github.com/verilator/verilator On the hardware synthesis side some exciting developments are also happening, mostly driven by the desire of companies like Google to be vendor independent for their Deep learning accelerator designs and through funding by DARPA.

In Running a Unix-like OS on a home-built CPU with a home-built C compiler

nickik·Jul 8, 2020

The 'original' RISC-V core was called Rocket. https://github.com/chipsalliance/rocket-chip So they picked a European rocket as a name.

In Ariane RISC-V CPU – An open source CPU capable of booting Linux

seldridge·Jul 7, 2020

I'm one of the Chisel devs. My biased view is that iterative development with Chisel, to the point of functional verification, is going to be faster than in a traditional RTL language primarily because you have a robust unit testing framework for Scala (Scalatest) and a library for testing Chisel hardware, ChiselTest [^1]. Basically, adopting test driven development is zero-cost---most Chisel users are writing tests as they're designing hardware. Note that there are existing options that help bridge this gap for Verilog/VHDL like VUnit [^2] and cocotb [^3]. For libraries, there's multiple levels. The Chisel standard library is providing basic hardware modules, e.g., queues, counters, arbiters, delay pipes, and pseudo-random number generators, as well as common interfaces, e.g., valid and ready/valid. Then there's an IP contributions repo

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(motivated by something like the old tensorflow contrib package) where people can add third-party larger IP [^4]. Then there's the level of standalone large IP built using Chisel that you can use like the Rocket Chip RISC-V SoC generator [^5], an OpenPOWER microprocessor [^6], or a systolic array machine learning accelerator [^7]. There are comparable efforts for building standard libraries in SystemVerilog, notably BaseJump STL [^8], though SystemVerilog's limited parameterization and lack of parametric polymorphism limit what's possible. You can also find lots of larger IP ready to use in traditional languages, e.g., a RISC-V core [^9]. Just because the user base of traditional languages is larger, you'll likely find more IP in those languages. [^1]: https://github.com/ucb-bar/chisel-testers2 [^2]: https://vunit.github.io/ [^3]: https://docs.cocotb.org/en/latest/ [^4]: https://github.com/freechipsproject/ip-contributions [^5]: https://github.com/chipsalliance/rocket-chip [^6]: https://github.com/antonblanchard/chiselwatt [^7]: https://github.com/ucb-bar/gemmini [^8]: https://github.com/bespoke-silicon-group/basejump_stl [^9]: https://github.com/openhwgroup/cva6

In Google offers free fabbing for 130nm open-source chips

seldridge·Oct 24, 2019

Thanks for taking a look at Chisel and FIRRTL! (Coming from a Chisel/FIRRTL dev...) Couple of clarifying comments: CDE[^1] is really a Rocket Chip[^2] specific design decision meant to suit the configuration needs of system-on-chip generation (or: it's a Scala library which actually doesn't depend on Chisel and could be useful in unrelated projects). Also, SiFive should have fixed the issues with exceptions a long while ago (stack traces are still a thing, though). Chisel gets a lot of criticism due to the (necessary) complexities of Rocket Chip. However, don't let that dissuade you from using it for a separate digital design project. None of the Rocket Chip complexity comes into play there. Compilation time is something that we really care about and are seeking to make better. Minute-long Verilog generation times are something you would

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only see for mammoth design like Rocket Chip (generating MBs of Verilog). Nonetheless, we have some ideas on how to improve this via actual optimizations or meta-optimizations like grouping compiler transformations together that are safe to do so. We also are really trying to make the Verification easier. One of these is effort on better testing via "Testers2"[^3] (name is TBD). The second is on improving the readability of the generated Verilog, e.g., emission of case statements [^4], emission of else-if[^5] (now supported!), etc. If you have suggestions we'd be happy to take a look (code examples of "I got this, but I'd like that" would be a huge plus, too!). Regardless, thanks for taking the time to check it out. [^1]: https://github.com/chipsalliance/api-config-chipsalliance [^2]: https://github.com/chipsalliance/rocket-chip [^3]: https://github.com/ucb-bar/chisel-testers2 [^4]: https://github.com/freechipsproject/chisel3/issues/1198 [^5]: https://github.com/freechipsproject/firrtl/pull/1204

In Chisel/FIRRTL Hardware Compiler Framework

rwmj·Oct 13, 2019

RocketChip would be the obvious choice. You can run it (somewhat slowly) on an FPGA. https://github.com/chipsalliance/rocket-chip

In SerenityOS: From Zero to HTML in a Year

rwmj·Feb 9, 2019

It's also about friction. You can download the RISC-V design straight off github (https://github.com/freechipsproject/rocket-chip) and start using it immediately. You don't have to phone up ARM or bring in lawyers to negotiate a license.

In Building a RISC-V PC

sitkack·Jan 27, 2019

The error is understandable, the main prototype RISC-V core is written in Chisel and the "Rocket Core Generator" is written in Chisel. The RISC-V team at Berkeley has a lot of overlap with the Chisel team. So it is easy to think RISC-V is all Chisel. I believe Chisel, Chisel, RISC-V, Chisel, if that makes any sense. https://riscv.org/wp-content/uploads/2015/01/riscv-rocket-ch... https://github.com/freechipsproject/rocket-chip (parametric SoC generator, Chisel) https://github.com/ucb-bar/riscv-sodor (Chisel) https://chisel.eecs.berkeley.edu/

In Verilog sources for Western Digital's open source RISC-V core

jamesaross·Dec 21, 2018

I wrote a short paper for HPEC that included some power and performance benchmarks and analysis on the HiFive Unleashed U540 SoC [0]. The SoC isn't open source as some suggest although I believe the core is based on the open source Rocket Chip Generator [1]. It seems the greatest weakness was in the slow memory interface. The details of memory controller and configuration were proprietary when I tried to find out why it wasn't performing well. [0] http://www.ieee-hpec.org/2018/2018program/index_htm_files/15... [1] https://github.com/freechipsproject/rocket-chip

In Porting Alpine Linux to RISC-V

nickik·Sep 26, 2018

You should checkout Chisel. https://chisel.eecs.berkeley.edu/ Its a HDL in Scala. It used extensively by Berkeley for things like the Open-Source RISC-V Rocket and Boom SoC chips. There are lots of projects based on it and you have some of the best open-source cores implemented in it. See: - https://github.com/freechipsproject/rocket-chip - https://github.com/ucb-bar/riscv-boom

In Designing a RISC-V CPU in VHDL: Arty S7 RPU SoC

rwmj·Jul 11, 2018

ARM are not worried that RISC-V will replace Cortex-A72. They license far more (by quantity and value) of the tiny Cortex-M embedded cores, and RISC-V can already replace just about every use of Cortex-M. The foolishness of this website was ARM telling everyone that RISC-V is a viable alternative. It could only have been worse if they'd provided a link to https://github.com/freechipsproject/rocket-chip

In Arm kills off its anti-RISC-V site after own staff revolt

tonmoy·Jan 3, 2018

This is not something new, Chisel is fairly mature by now. Chisel was made by the same people who created RISCV based rocket chip. In fact rocket chip is written using Chisel https://github.com/freechipsproject/rocket-chip

In Chisel: Constructing Hardware in a Scala Embedded Language

gioele·Oct 7, 2017

Previous discussion: https://news.ycombinator.com/item?id=15400217 > I understand the ISA is open source, but SiFive does appear to be selling their IP. > > https://dev.sifive.com/coreplex-risc-v-ip/buy/ IIUC, SiFive is selling the ready-made "hard IP" [1], that means a compiled netlist that has been laid out at a slightly-abstract-but-almost-mask level. All this is manual work done on top of a netlist generated using the open-source Rocket chip generator [2,3] (SiFive people contribute to the upstream repository). Let's make a Wordpress analogy: SiFive is a big contributor to Wordpress and does most of the work upstream. At the same time they sell you preconfigured server images for your blog with Wordpress, nginx, varnish and postfix almost ready to go (few settings like IP, hostname and WP theme are still missing). [1] https://en.wiki

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pedia.org/wiki/Semiconductor_intellectual_pro... [2] https://bar.eecs.berkeley.edu/projects/2014-rocket_chip.html [3] https://github.com/freechipsproject/rocket-chip

In Linux Now Has Its First Open Source RISC-V Processor

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