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chipsalliance
rocket-chip
Scala2017–2025
chipsalliance / rocket-chip

rocket-chip

Rocket Chip Generator

Hardware & Embedded
Explore on GitHubRead Hacker News discussions
12Distinct people
18Mentions
0Explicit recommenders
3.9KGitHub stars
REPOSITORY AT A GLANCE

What to know before exploring

What it is

Rocket Chip Generator

GitHub

Where it is used

No documented product use was verified in the last source check.

What people are saying

No recommendation phrase was found in the indexed comments.

No classified warning is attached to this page. Read the discussions before treating silence as approval.

Also in these discussions

Mentioned in the same Hacker News threads. That is not proof they are substitutes.

This week on Hacker News

Nov 8–Nov 15 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/15/2026, 7:02:26 AM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by year18 dated mentions

Observed mentions: 2017-06-27 08:22:56 UTC to 2025-10-29 15:40:56 UTC.

012342017-01-01 00:00:00 UTC to 2018-01-01 00:00:00 UTC (exclusive): 4 mentions; 0 submissions, 4 comments20172018-01-01 00:00:00 UTC to 2019-01-01 00:00:00 UTC (exclusive): 4 mentions; 0 submissions, 4 comments2019-01-01 00:00:00 UTC to 2020-01-01 00:00:00 UTC (exclusive): 4 mentions; 0 submissions, 4 comments2020-01-01 00:00:00 UTC to 2021-01-01 00:00:00 UTC (exclusive): 3 mentions; 0 submissions, 3 comments2021-01-01 00:00:00 UTC to 2022-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments20212022-01-01 00:00:00 UTC to 2023-01-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 comments2023-01-01 00:00:00 UTC to 2024-01-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 comments2024-01-01 00:00:00 UTC to 2025-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2025-01-01 00:00:00 UTC to 2026-01-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 comments2025

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

View mention counts and date ranges
UTC ranges include their start and exclude their end. Select a period to filter the source evidence.
PeriodStart (UTC)End (exclusive, UTC)MentionsSubmissionsComments
20172017-01-01 00:00:00 UTC2018-01-01 00:00:00 UTC404
20182018-01-01 00:00:00 UTC2019-01-01 00:00:00 UTC404
20192019-01-01 00:00:00 UTC2020-01-01 00:00:00 UTC404
20202020-01-01 00:00:00 UTC2021-01-01 00:00:00 UTC303
20212021-01-01 00:00:00 UTC2022-01-01 00:00:00 UTC000
20222022-01-01 00:00:00 UTC2023-01-01 00:00:00 UTC101
20232023-01-01 00:00:00 UTC2024-01-01 00:00:00 UTC101
20242024-01-01 00:00:00 UTC2025-01-01 00:00:00 UTC000
20252025-01-01 00:00:00 UTC2026-01-01 00:00:00 UTC101

What Hacker News says

4 sources
gioele·Oct 7, 2017
Previous discussion: https://news.ycombinator.com/item?id=15400217 > I understand the ISA is open source, but SiFive does appear to be selling their IP. > > https://dev.sifive.com/coreplex-risc-v-ip/buy/ IIUC, SiFive is selling the ready-made "hard IP" [1], that means a compiled netlist that has been laid out at a slightly-abstract-but-almost-mask level. All this is manual work done on top of a netlist generated using the open-source Rocket chip generator [2,3] (SiFive people contribute to the upstream repository). Let's make a Wordpress analogy: SiFive is a big contributor to Wordpress and does most of the work upstream. At the same time they sell you preconfigured server images for your blog with Wordpress, nginx, varnish and postfix almost ready to go (few settings like IP, hostname and WP theme are still missing). [1] https://en.wiki
Read the rest
pedia.org/wiki/Semiconductor_intellectual_pro... [2] https://bar.eecs.berkeley.edu/projects/2014-rocket_chip.html [3] https://github.com/freechipsproject/rocket-chip
In Linux Now Has Its First Open Source RISC-V Processor
orbifold·Oct 1, 2017
Regarding the ASIC part: There are several good courses online that explain the whole process from hardware description in a hardware description language to GDSII file, which you could send to a foundry in some detail. See for example this course https://web.csl.cornell.edu/courses/ece5745/, there are also very good courses available from Berkeley and MIT. What is usually missing is the more gory details of the backend flow, which can become very involved and complicated depending on your design and process. Unfortunately someone who has no access to the EDA tools by cadence / synopsis or standard library files from foundries, cannot really follow along all that far, you are limited to working at the RTL level. There are several good open source RTL simulators available, I have personally used mostly verilator, which supports (almost) al
Read the rest
l synthesizable constructs of system verilog and has performance close to the best commercial simulators like vcs. It compiles your design to C++ code which you can then wrap in any way you like. You should also check out https://chisel.eecs.berkeley.edu/, which is a hardware description language embedded in scala, the nice thing about it is that it has a relatively large number of high quality open source examples, designs (https://github.com/freechipsproject/rocket-chip) and a library of standard components available, something which can't really be said of verilog / vhdl unfortunately. As an added bonus you can actually use IntelliJ as an IDE, which blows any of the commercial IDEs available for system verilog or vhdl out of the water. Another thing I can recommend is to get yourself a cheap FPGA board, some of them are programmable purely with open source tools, see http://www.clifford.at/icestorm/. Alternatively the Arty Devkit comes with a license for the Xilinx Vivado toolchain.
In Ask HN: Where do I get started on ASICs, FPGA, RTL, Verilog et. al?
peller·Sep 20, 2017
I have no experience with any of this, but to my knowledge what you're looking for is the Rocket Chip.[0] It's a RISC-V core implemented in Chisel. The primary FPGA target is a bit steep at around $500 [1] but there's a "small" config[2] that targets a more reasonable $190 board [3]. [0] https://github.com/freechipsproject/rocket-chip [1] http://store.digilentinc.com/zedboard-zynq-7000-arm-fpga-soc... [2] https://github.com/freechipsproject/rocket-chip#-how-can-i-p... [3] http://store.digilentinc.com/zybo-zynq-7000-arm-fpga-soc-tra...
In A smaller, cheaper RISC V board
jackckang·Jun 27, 2017
Sorry to hear that you're feeling dejected. On your questions: 1) We are providing FE310 samples to folks who ask us for them at info@sifive.com See our past forum posts for similar requests: https://forums.sifive.com/t/assistance-getting-in-contact-wi... https://forums.sifive.com/t/e300-on-the-market-other-sbc-s-w... 2) We do provide both versions, just as you recommended. SiFive continues to maintain the Rocket repository at https://github.com/freechipsproject/rocket-chip We intend to continue to maintain this core and ensure it's compatible with any updates to the RISC-V specification. For commercial customers who do not want to utilize rocket-chip, we are providing them with other options. -Jack (from SiFive)
In 6th RISC-V Workshop Proceedings

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