rocket-chip

Thanks for taking a look at Chisel and FIRRTL! (Coming from a Chisel/FIRRTL dev...) Couple of clarifying comments: CDE[^1] is really a Rocket Chip[^2] specific design decision meant to suit the configuration needs of system-on-chip generation (or: it's a Scala library which actually doesn't depend on Chisel and could be useful in unrelated projects). Also, SiFive should have fixed the issues with exceptions a long while ago (stack traces are still a thing, though). Chisel gets a lot of criticism due to the (necessary) complexities of Rocket Chip. However, don't let that dissuade you from using it for a separate digital design project. None of the Rocket Chip complexity comes into play there. Compilation time is something that we really care about and are seeking to make better. Minute-long Verilog generation times are something you would

RocketChip would be the obvious choice. You can run it (somewhat slowly) on an FPGA. https://github.com/chipsalliance/rocket-chip

It's also about friction. You can download the RISC-V design straight off github (https://github.com/freechipsproject/rocket-chip) and start using it immediately. You don't have to phone up ARM or bring in lawyers to negotiate a license.

The error is understandable, the main prototype RISC-V core is written in Chisel and the "Rocket Core Generator" is written in Chisel. The RISC-V team at Berkeley has a lot of overlap with the Chisel team. So it is easy to think RISC-V is all Chisel. I believe Chisel, Chisel, RISC-V, Chisel, if that makes any sense. https://riscv.org/wp-content/uploads/2015/01/riscv-rocket-ch... https://github.com/freechipsproject/rocket-chip (parametric SoC generator, Chisel) https://github.com/ucb-bar/riscv-sodor (Chisel) https://chisel.eecs.berkeley.edu/