rocket-chip

ling around Chisel or various scattered libraries of open-source components which are often hard to get to work together, but also this requires a massive amount of time investment to just get the synthesis / simulation flow working. The situation is slowly improving and there are various university research groups and corporations that have released larger amounts of open source code that one can use as a starting point: - https://github.com/openhwgroup/cva6 (mostly done by ETHZ people initially, also see https://github.com/pulp-platform/pulpino) - https://github.com/chipsalliance/Cores-SweRV-EL2 (one of several high quality open-source RISC-V cores by Western Digital) - https://github.com/chipsalliance/rocket-chip (UCB by initial creators of RISC-V) - https://github.com/electronicvisions/nux (POWER based embedded processor, that we have used in several neuromorphic chip tapeouts (silicon proven)) On the tooling side one great thing that happened is that the verilator open source simulator has gained a lot of traction. - https://github.com/verilator/verilator On the hardware synthesis side some exciting developments are also happening, mostly driven by the desire of companies like Google to be vendor independent for their Deep learning accelerator designs and through funding by DARPA.

(motivated by something like the old tensorflow contrib package) where people can add third-party larger IP [^4]. Then there's the level of standalone large IP built using Chisel that you can use like the Rocket Chip RISC-V SoC generator [^5], an OpenPOWER microprocessor [^6], or a systolic array machine learning accelerator [^7]. There are comparable efforts for building standard libraries in SystemVerilog, notably BaseJump STL [^8], though SystemVerilog's limited parameterization and lack of parametric polymorphism limit what's possible. You can also find lots of larger IP ready to use in traditional languages, e.g., a RISC-V core [^9]. Just because the user base of traditional languages is larger, you'll likely find more IP in those languages. [^1]: https://github.com/ucb-bar/chisel-testers2 [^2]: https://vunit.github.io/ [^3]: https://docs.cocotb.org/en/latest/ [^4]: https://github.com/freechipsproject/ip-contributions [^5]: https://github.com/chipsalliance/rocket-chip [^6]: https://github.com/antonblanchard/chiselwatt [^7]: https://github.com/ucb-bar/gemmini [^8]: https://github.com/bespoke-silicon-group/basejump_stl [^9]: https://github.com/openhwgroup/cva6