NAnamanyayg·Feb 3, 2025Submission
T1: A RISC-V Vector processor implementation
117 points · Open discussionchipsalliance
t1
Scala2024–2025
chipsalliance / t1
t1
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| Period | Start (UTC) | End (exclusive, UTC) | Mentions | Submissions | Comments |
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| Apr 2024 | 2024-04-01 00:00:00 UTC | 2024-05-01 00:00:00 UTC | 1 | 0 | 1 |
| May 2024 | 2024-05-01 00:00:00 UTC | 2024-06-01 00:00:00 UTC | 0 | 0 | 0 |
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| Sep 2024 | 2024-09-01 00:00:00 UTC | 2024-10-01 00:00:00 UTC | 0 | 0 | 0 |
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| Feb 2025 | 2025-02-01 00:00:00 UTC | 2025-03-01 00:00:00 UTC | 1 | 1 | 0 |
What Hacker News says
2 sourcesYou seem to be confusing two different things:
gravitron: has ARM SVE extension
licheerv nano: has RISC-V Vector extension
Both ARM SVE and the RISC-V Vector Extension (RVV) are vector length agnostic, but quite different in their design.
Since RISC-V allows for open source implementations, there are a few projects working on RVV implementations.
Check out the t1 project, they implement a configurable RVV implementation, that is supposed to be driven by a small scalar core, e.g. RocketChip. [0]
There are configurations for vector length of 512-bit to 16K bit.
Connecting it to RocketChip isn't officially supported just yet, and it uses the spike emulator for the scalar part.
They offer a pre-build docker environment, so you can play around with the RTL simulation via
"docker run --name t1 -it -v $PWD:/workspace --rm ghcr.io/chipsalliance/t
Read the rest
1-machamp:latest /bin/bash"
This drops you into a shell, and you can start simulating a 1K vector length processor, with "ip-emulator --no-logging -C yourProgram", see the tests/ director for example code.
At least in theory, but there might still be a few bugs.
[0] https://github.com/chipsalliance/t1