verible

FWIW Google is working on improving the support for SystemVerilog in open source tools. On the developer tooling side, there is https://github.com/google/verible for linting, code formatting and code indexing. On the actual compilation side with there are https://github.com/alainmarcel/Surelog and https://github.com/alainmarcel/UHDM which are then being coupled with open source tools like Yosys to allow targeting Xilinx 7 Series and Lattice ECP5 FPGA ICs with fully open source flows using fully open source FPGA tools like symbiflow.github.io

> Want a linter for your project? That's going to be $50k Another interesting open source EDA project coming out of Google is Verible: https://github.com/google/verible which provides Verilog linting amongst other things.