riscv-formal

Again, being able to spin your own chips isn't really at issue here, that's already possible. ARM and MIPS will likely happily let you continue to make chips based on old cores as long as you continue to pay your license fees. The freedoms from the Open Source model is substantial enough to make it attractive on that basis alone, just as for Linux/BSD. One example is Western Digital transitioning to RISC-V for their hard drive controllers. I would imagine being able to add your own instructions without having to deal with NDAs and non competes with ARM will be attractive to a lot of OEMs. Just like with Linux, it's difficult to anticipate what intersting things will come out of RISC-V, but one interesting example is a formally verified RISC-V core, picorv32: https://github.com/cliffordwolf/riscv-formal/tree/master/cor... (presentation he

Why not picorv32? Size-optimized, open licensed (no 64-bit, but that's where you could come in and be a star!) Clifford Wolf, the author, also wrote Yosys and Icestorm, which you can use to synthesize picorv32 for the iCE40 FPGAs with a fully open source HDL toolchain. It's really nice and usable! Clifford has also been doing a lot of cool work adding SMT-based verification tech for synthesis via Yosys, and even started working on a verification bench for RISC-V implementations: https://github.com/cliffordwolf/riscv-formal - he's also very nice and approachable IMO. I'm sure he'd appreciate some extra help. Sounds like exactly what you want, perhaps.