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cliffordwolf
riscv-formal
Verilog2017–2018
cliffordwolf / riscv-formal

riscv-formal

RISC-V Formal Verification Framework

Hardware & Embedded
Explore on GitHubRead Hacker News discussions
2Distinct people
2Mentions
0Explicit recommenders
5GitHub stars
REPOSITORY AT A GLANCE

What to know before exploring

What it is

RISC-V Formal Verification Framework

GitHub

Where it is used

No documented product use has been verified yet.

What people are saying

No recommendation phrase was found in the indexed comments.

No classified warning is attached to this page. Read the discussions before treating silence as approval.

Also in these discussions

No other repository is repeatedly linked in the same discussions.

This week on Hacker News

Nov 8–Nov 15 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/15/2026, 9:28:18 AM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by month2 dated mentions

Observed mentions: 2017-01-12 15:04:02 UTC to 2018-07-09 17:36:44 UTC.

012017-01-01 00:00:00 UTC to 2017-02-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 commentsJan 20172017-02-01 00:00:00 UTC to 2017-03-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2017-03-01 00:00:00 UTC to 2017-04-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2017-04-01 00:00:00 UTC to 2017-05-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2017-05-01 00:00:00 UTC to 2017-06-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2017-06-01 00:00:00 UTC to 2017-07-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2017-07-01 00:00:00 UTC to 2017-08-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2017-08-01 00:00:00 UTC to 2017-09-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2017-09-01 00:00:00 UTC to 2017-10-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2017-10-01 00:00:00 UTC to 2017-11-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 commentsOct 20172017-11-01 00:00:00 UTC to 2017-12-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2017-12-01 00:00:00 UTC to 2018-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2018-01-01 00:00:00 UTC to 2018-02-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2018-02-01 00:00:00 UTC to 2018-03-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2018-03-01 00:00:00 UTC to 2018-04-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2018-04-01 00:00:00 UTC to 2018-05-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2018-05-01 00:00:00 UTC to 2018-06-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2018-06-01 00:00:00 UTC to 2018-07-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2018-07-01 00:00:00 UTC to 2018-08-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 commentsJul 2018

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

View mention counts and date ranges
UTC ranges include their start and exclude their end. Select a period to filter the source evidence.
PeriodStart (UTC)End (exclusive, UTC)MentionsSubmissionsComments
Jan 20172017-01-01 00:00:00 UTC2017-02-01 00:00:00 UTC101
Feb 20172017-02-01 00:00:00 UTC2017-03-01 00:00:00 UTC000
Mar 20172017-03-01 00:00:00 UTC2017-04-01 00:00:00 UTC000
Apr 20172017-04-01 00:00:00 UTC2017-05-01 00:00:00 UTC000
May 20172017-05-01 00:00:00 UTC2017-06-01 00:00:00 UTC000
Jun 20172017-06-01 00:00:00 UTC2017-07-01 00:00:00 UTC000
Jul 20172017-07-01 00:00:00 UTC2017-08-01 00:00:00 UTC000
Aug 20172017-08-01 00:00:00 UTC2017-09-01 00:00:00 UTC000
Sep 20172017-09-01 00:00:00 UTC2017-10-01 00:00:00 UTC000
Oct 20172017-10-01 00:00:00 UTC2017-11-01 00:00:00 UTC000
Nov 20172017-11-01 00:00:00 UTC2017-12-01 00:00:00 UTC000
Dec 20172017-12-01 00:00:00 UTC2018-01-01 00:00:00 UTC000
Jan 20182018-01-01 00:00:00 UTC2018-02-01 00:00:00 UTC000
Feb 20182018-02-01 00:00:00 UTC2018-03-01 00:00:00 UTC000
Mar 20182018-03-01 00:00:00 UTC2018-04-01 00:00:00 UTC000
Apr 20182018-04-01 00:00:00 UTC2018-05-01 00:00:00 UTC000
May 20182018-05-01 00:00:00 UTC2018-06-01 00:00:00 UTC000
Jun 20182018-06-01 00:00:00 UTC2018-07-01 00:00:00 UTC000
Jul 20182018-07-01 00:00:00 UTC2018-08-01 00:00:00 UTC101

What Hacker News says

1 sources
aseipp·Jan 12, 2017
Why not picorv32? Size-optimized, open licensed (no 64-bit, but that's where you could come in and be a star!) Clifford Wolf, the author, also wrote Yosys and Icestorm, which you can use to synthesize picorv32 for the iCE40 FPGAs with a fully open source HDL toolchain. It's really nice and usable! Clifford has also been doing a lot of cool work adding SMT-based verification tech for synthesis via Yosys, and even started working on a verification bench for RISC-V implementations: https://github.com/cliffordwolf/riscv-formal - he's also very nice and approachable IMO. I'm sure he'd appreciate some extra help. Sounds like exactly what you want, perhaps.
In RISC-V port submitted for inclusion in GCC

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