HackerReposA FIELD GUIDE TO OPEN SOURCE
ProSponsor the shelf♧ 0
← Back to top all-time
efabless
caravel
Verilog2020–2026
efabless / caravel

caravel

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

4Distinct people
5Mentions
0Explicit recommenders
421GitHub stars
REPOSITORY AT A GLANCE

What to know before exploring

What it is

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

GitHub

Where it is used

No documented product use has been verified yet.

What people are saying

No recommendation phrase was found in the indexed comments.

No classified warning is attached to this page. Read the discussions before treating silence as approval.

Also in these discussions

No other repository is repeatedly linked in the same discussions.

This week on Hacker News

Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 3:56:07 PM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by year5 dated mentions

Observed mentions: 2020-11-21 21:34:27 UTC to 2026-03-15 05:52:32 UTC.

012342020-01-01 00:00:00 UTC to 2021-01-01 00:00:00 UTC (exclusive): 4 mentions; 0 submissions, 4 comments20202021-01-01 00:00:00 UTC to 2022-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2022-01-01 00:00:00 UTC to 2023-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2023-01-01 00:00:00 UTC to 2024-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments20232024-01-01 00:00:00 UTC to 2025-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2025-01-01 00:00:00 UTC to 2026-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2026-01-01 00:00:00 UTC to 2027-01-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 comments. Incomplete calendar period.2026*

* An incomplete calendar period is marked with an outlined bar. Its count is not directly comparable with a full period.

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

View mention counts and date ranges
UTC ranges include their start and exclude their end. Select a period to filter the source evidence.
PeriodStart (UTC)End (exclusive, UTC)MentionsSubmissionsComments
20202020-01-01 00:00:00 UTC2021-01-01 00:00:00 UTC404
20212021-01-01 00:00:00 UTC2022-01-01 00:00:00 UTC000
20222022-01-01 00:00:00 UTC2023-01-01 00:00:00 UTC000
20232023-01-01 00:00:00 UTC2024-01-01 00:00:00 UTC000
20242024-01-01 00:00:00 UTC2025-01-01 00:00:00 UTC000
20252025-01-01 00:00:00 UTC2026-01-01 00:00:00 UTC000
2026 (partial)2026-01-01 00:00:00 UTC2027-01-01 00:00:00 UTC101

What Hacker News says

5 sources
In the space of possibilities this can be abstractly thought of as a Caravell [1] harness gone wild. But if you had to price access to the project in a commercial sense, then, the pricing is going to be quite high. Because it's not just the cost of the masks - there's a whole lot of talent and skill in the team that does the "backend" processing. That is, once the RTL is done, it goes through multiple passes of place/route/timing, ATPG, DRC, LVS...and that's just to get to the tape-out. After that there's still more to do with the chip probe, packaging and reeling. The open-source argument is that if we could make that back-end part more transparent, then, we could improve the tooling and thus decrease the labor. But, even a single mistake at these backend steps can scuttle a whole mask set. The methodology is incredibly incremental, scri
Read the rest
pts are handed down for generations and there are magic settings in them that make things "just work" and nobody quite remembers why or how but it was probably a lesson learned the hard way so we just leave it that way. And it's not just the money - the iteration time through a fab is months. So you have to be a bit careful about prioritizing your experiments and your risk budget when trying to make progress in this field. I am lucky in my case because what I want to do aligns with their original commercial interests, so the strategic benefit makes things worth the tactical risk. Frankly a big part of the project overall was just figuring out how to scope things so that we both came away reasonably satisfied in terms of risk and outcomes. Would I like things to be more open? yes. would I liked to have put an opentitan core in there? yes. Would I have been able to take advantage of more back-end support to do a faster CPU? yes. But, we had to constantly balance tactical risks, and even if I don't agree with all their decisions, I have to respect their experience. [1] https://github.com/efabless/caravel
In Baochip-1x: What it is, why I'm doing it now and how it came about
Those pins are not connected to the external package. See page 4 of the Caravel datasheet here: https://github.com/efabless/caravel/blob/master/doc/caravel_datasheet.pdf Only the digital I/Os are accessible from outside the package. Every entry in the table has either "power", "ground", or "digital {in,out,I/O}" for the "type" column. They appear to have some kind of simple output-only analog driver (see "analog output" in the Summary Description column) but no analog input according to the datasheet.
In Google partners with SkyWater to enable open source manufacturing of ASICs
I have checked again. To get analog io, projects can connect to the analog_io pins in the wrapper [1] which connect to the pad through a 150 ohm resistor, and disable the digital GPIO drivers. If that resistor is a problem, user projects can route directly to the pad_no_esd pin. There are a number of people working on analog or mixed-signal designs inside the caravel harness with analog io. From caravel/verilog/rtl/README: > mprj_io: 32 bits general purpose programmable digital or analog I/O > The user will also have access to the ESD-protected pad connections for analog signals [1] https://github.com/efabless/caravel/blob/c4c79cdf63d6a7ed7ce...
In Google partners with SkyWater to enable open source manufacturing of ASICs
I've been following this closely and put a fair bit of time into porting a CAD tool to this new process. I won't be submitting a design at this time. The Google sponsorship comes with a lot of strings attached. That's okay, "he who pays the piper calls the tune". Unfortunately unlike MOSIS and IMEC there is no option to pay your own way in order to drop the strings. Based on MPW charges for other foundries through MOSIS+IMEC the Google subsidy is worth around $5k-$10k per submission [1]. But there isn't any option to pay that amount yourself. One of the most problematic "strings" is the fact that you do NOT get a reserved booking. This is a big issue because for anything more serious than an undergrad-level "hey I threw a pile of verilog at the place+route tool" the designer time invested will be worth a lot more than $5k-$10k. But
Read the rest
they expect you to invest this with zero guarantee of getting it fabbed, which means that investment can easily get dumped in the trash bin. Project selection is "random" which is sort of just another way of saying "unaccountable". The other problematic "string" is the Management Engine Padframe [2] they wrap around your design. You can't touch it or change any part of it, and it sits beteween your design and every single pad that faces the outside world. This sort of Management Engine garbage is exactly what we need open silicon in order to avoid. Yet here Google and Skywater and eFabless are sticking it back into the mix. Oh, by the way, this makes "OpenMPW" totally unusable for any RF work, or any design that needs an analog input. Kinda miffed about all this, especially that they sprung the "Management Padframe" on us two weeks before the tapeout deadline. That screams to me "this is not for serious designs, please undergrads only thanks". [1] https://europractice-ic.com/schedules-prices/ [2] https://github.com/efabless/caravel PS, It's also intensely irritating that you're forced to create a LinkedIn account and must use your LinkedIn account to log in to the MPW upload site. That is some amateur-grade personal data harvesting there. Serious MPW providers, like MOSIS who have been doing this for 25 years, give you their PGP key for you to encrypt the GDS with and don't put you at the mercy of deplatforming by LinkedIn for whatever lame reason LinkedIn cooked up this week.
In Google partners with SkyWater to enable open source manufacturing of ASICs
It looks like you're using an ice40 FPGA? If you can make your project work with 38 I/O pins you could probably get it fabricated in ASIC by Efabless free. You just need to meet their repository requirements and make your verilog module conform to this interface: https://github.com/efabless/caravel/blob/master/verilog/rtl/... The openlane tool converts your verilog all the way down to final ASIC design... You'd need to license everything Apache 2.0 though. And it would have to be done soon, the deadline is Nov 30th.
In I'm building a Minecraft clone in hardware, on a tiny FPGA with 143kb of RAM

MAKE YOURSELF AT HOME

A few shortcuts

/
Search the collection
?
Open this guide
Esc
Close dialogs and navigation

Your saved repositories and interests stay in this browser.