TVtverbeure·Sep 27, 2025
LiteX has been a digital SOC IP library for man years.
https://github.com/enjoy-digital/litex
In Litex: The First Formal Language Learnable in 1-2 Hoursenjoy-digital
litex
Python2019–2025
enjoy-digital / litex
litex
Build your hardware, easily!
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Build your hardware, easily!
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Most popular modern SoCs are not fully documented - one part that usually lacks any documentation is the GPU. For most ARM-based SoCs, it's either one of ARM's Mali series or…
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This week on Hacker News
Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 3:56:07 PM UTC.
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HN mentions by year19 dated mentions
Observed mentions: 2019-09-25 04:25:00 UTC to 2025-09-27 08:39:00 UTC.
Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.
View mention counts and date ranges
| Period | Start (UTC) | End (exclusive, UTC) | Mentions | Submissions | Comments |
|---|---|---|---|---|---|
| 2019 | 2019-01-01 00:00:00 UTC | 2020-01-01 00:00:00 UTC | 2 | 1 | 1 |
| 2020 | 2020-01-01 00:00:00 UTC | 2021-01-01 00:00:00 UTC | 3 | 1 | 2 |
| 2021 | 2021-01-01 00:00:00 UTC | 2022-01-01 00:00:00 UTC | 4 | 0 | 4 |
| 2022 | 2022-01-01 00:00:00 UTC | 2023-01-01 00:00:00 UTC | 5 | 1 | 4 |
| 2023 | 2023-01-01 00:00:00 UTC | 2024-01-01 00:00:00 UTC | 3 | 0 | 3 |
| 2024 | 2024-01-01 00:00:00 UTC | 2025-01-01 00:00:00 UTC | 1 | 0 | 1 |
| 2025 | 2025-01-01 00:00:00 UTC | 2026-01-01 00:00:00 UTC | 1 | 0 | 1 |
What Hacker News says
19 sourcesMost popular modern SoCs are not fully documented - one part that usually lacks any documentation is the GPU. For most ARM-based SoCs, it's either one of ARM's Mali series or an Imagination Technologies product, most RISC-V based SoCs (e.g. the JH7110) also use Imagination Technologies GPUs.
Additional components also have documentation that's hard to find, especially those based on Synopsys' DesignWare IP. These are sometimes at least... strange (or should I say buggy?) effects such as with their "standard" 16550-compatible UART: https://lupyuen.github.io/articles/plic
The Vivante GPU in Freescale's i.MX8 SoCs was reverse engineered and is probably the closest you can find to a somewhat documented GPU (STM32MP SoCs also have a Vivante GPU). In general, the i.MX8 is well documented - one of the reasons why it is used in Purism's Librem 5
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phone.
You can "cheat" and improve the GPU situation a bit by using a RISC-V board with a PCIe slot and an old AMD GPU.
When there's no documentation available, all you can do is reverse engineer the functionality of existing open source drivers. Linux drivers are often quite complex, I recommend looking at Net/OpenBSD and Plan9 drivers instead. For some RISC-V SoCs (SiFive Freedom U740 on the Unmatched board and JH7110), Haiku is also worth looking at.
An alternative which provides documented hardware is to use an FPGA-based SoC builder, e.g. LiteX: https://github.com/enjoy-digital/litex
Of course, this results in a significant degradation of performance...
Another option would be to use a regular x86-based PC and rely on the documented interfaces, such as VESA graphics, but then you have to deal with x86 and all the baggage of almost 45 years of PC evolution...
https://github.com/enjoy-digital/litex
they have tutorials, you can get compatible boards for around $20
In FPGA Dev Boards for $150 or LessThere is a ton of open source stuff these days see:
https://icestudio.io/
https://github.com/enjoy-digital/litex
https://github.com/os-fpga/open-source-fpga-resource
In FPGA Dev Boards for $150 or LessNothing is really comparable to the DE-10 Nano's combination of capacity, embedded ARM cores, memory, HDMI scaler, and (most importantly) price. The ZedBoard fails the last test: it is a fair bit more expensive than the Nano.
I am keen on the MiSTex project though. The plan is to come up with something that is more flexible than MiSTer to support different targets. So for example, you might be able to target a simpler core to a simpler device and vice versa.
https://github.com/MiSTeX-devel
https://github.com/enjoy-digital/litex
In AMD Introduces World’s Largest FPGA-Based Adaptive SoC for EmulationYes, you can use existing blocks and IPs.
E.g. if you use the f4pga+migen+LiteX stack, this looks like this in the end: https://github.com/enjoy-digital/litex/blob/d36f98bf45c20e2f...
In F4PGA: Open FPGA Tooling: Xilinx 7-Series, Lattice iCE40/ECP5, QuickLogic EOS S3> how to debug a non-working design
In LiteX, an open source toolset for making FPGA designs, you can embed an oscilloscope into your FPGA: https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To...
In Parallel Programming for FPGAshttps://github.com/enjoy-digital/litex/wiki/Use-LiteX-on-the...
Not equivalent to the Pi 4, but still runs linux. (the Acorn CLE is a rebadged NiteFury)
In NiteFury – An Artix-7 FPGA with its own DDR3 RAM right in your laptopCrypto-surplus hardware with same FPGA, https://www.hivelist.org/@apshamilton/acorn-215-xilinx-artix... & https://www.eevblog.com/forum/fpga/sqrl-acorn-as-an-interest...
Artix-7 is supported by LiteX, an open-source toolchain based on reverse engineering of Xilinx bitstream, https://github.com/enjoy-digital/litex & https://antmicro.com/blog/2020/05/multicore-vex-in-litex/
These can be used for PCILeech DMA attacks/testing, http://blog.frizk.net/2021/10/acorn.html
In NiteFury – An Artix-7 FPGA with its own DDR3 RAM right in your laptopIs it written in FORTH?
https://en.wikipedia.org/wiki/Open_Firmware
If you look at one of the earlier x-series servers- x3650-M1 I think, the BMC (IBM calls it an IMM) is daughter board with a PPC 405 chip. The artwork has "Proudly made in North Carolina" with a map of North Carolina in etch. You can just see it in the picture, under the "IBM":
https://admirestore.top/other/ibm-x3650-rsa-telecharger-pilo...
Anyway, I wonder if the code is related. I would have thought this all went to Lenovo.
What you really need for an open-source BMC, is one that works with the common Aspeed KVM chips (ARM-based I think, look at AST2300 and above). This would have the nice effect of avoiding having to pay AMI for their BMC code.
Edit: Actually here is the code, it supports Apseed:
https://github.com/openbmc/openbmc
What's new in LibreBMC is the hard
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ware toolchain. Frankly, they should target RISC-V for this. Edit again: it does, using LiteX:
https://github.com/enjoy-digital/litex
I'm not sure where Power fits in..
Sounds like nmigen might be a good open source successor to the project that you describe: https://github.com/nmigen/nmigen
There are lots of open-source (n)migen components available through the litex framework: https://github.com/enjoy-digital/litex
In Unifying the CUDA Python EcosystemI'm about 20kloc in to a (not public) nMigen project, including a UDP/IP stack, various peripheral drivers, a DSP pipeline, and some custom networking code. So far I think "do the advantages of being able to metaprogram outweigh..."is a resounding "yes", but I came to it with extensive Python experience so it feels like a very natural fit to me, and given how other attempts at embedded metaprogramming go (Tcl...) I'm not sure Python is easily beat. Being able to integrate with numpy for DSP work, pytest for simulation and testing, Python packaging (such as it is) for distributing modules and managing dependencies and versioning, and simulating inside Python too are all additional compelling advantages.
nMigen is a pretty fledgling project so there aren't a ton of big projects in it yet, but for example Luna[0] (from the makers of the Hack
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RF) implements a full USB stack including USB3 support, with enough abstraction that you can create a USB-serial converter inside your FPGA using two I/Os for full-speed USB and wire it into the rest of your project in about ten lines of Python[1].
[0]: https://github.com/greatscottgadgets/luna
[1]: https://github.com/greatscottgadgets/luna/blob/master/exampl...
Migen, the Python-based project nMigen is based off, has been around for longer and has some large projects, such as LiteX[2] which uses Migen to glue together entire SoCs, including peripheral cores such as GigE, DDR3/4, SATA, PCIe, etc, all written in Migen, and is pretty widely used. It also pulls in Verilog/VHDL designs (such as many of its CPU core choices) since it's easy to pull in those from the Python side.
[2]: https://github.com/enjoy-digital/litex/
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