fiberhood

MorphleLogic

Verilog2021–2026

fiberhood / MorphleLogic

MorphleLogic

Morphle Logic V1.0, an open hardware asynchronous runtime reconfigurable array ARRA or PPL,FPGA,CPLD

Languages & Compilers Hardware & Embedded

Explore on GitHub Read Hacker News discussions

2Distinct people

9Mentions

0Explicit recommenders

27GitHub stars

REPOSITORY AT A GLANCE

What to know before exploring

What it is

Morphle Logic V1.0, an open hardware asynchronous runtime reconfigurable array ARRA or PPL,FPGA,CPLD

GitHub

Where it is used

No documented product use has been verified yet.

What people are saying

No recommendation phrase was found in the indexed comments.

No classified warning is attached to this page. Read the discussions before treating silence as approval.

Also in these discussions

No other repository is repeatedly linked in the same discussions.

This week on Hacker News

Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 3:03:16 PM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by year9 dated mentions

Observed mentions: 2021-05-21 20:19:42 UTC to 2026-05-23 12:42:15 UTC.

* An incomplete calendar period is marked with an outlined bar. Its count is not directly comparable with a full period.

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

View mention counts and date ranges

UTC ranges include their start and exclude their end. Select a period to filter the source evidence.
Period	Start (UTC)	End (exclusive, UTC)	Mentions	Comments
2021	2021-01-01 00:00:00 UTC	2022-01-01 00:00:00 UTC	1	1
2022	2022-01-01 00:00:00 UTC	2023-01-01 00:00:00 UTC	0	0
2023	2023-01-01 00:00:00 UTC	2024-01-01 00:00:00 UTC	2	2
2024	2024-01-01 00:00:00 UTC	2025-01-01 00:00:00 UTC	3	3
2025	2025-01-01 00:00:00 UTC	2026-01-01 00:00:00 UTC	1	1
2026 (partial)	2026-01-01 00:00:00 UTC	2027-01-01 00:00:00 UTC	2	2

What Hacker News says

9 sources

morphle·May 23, 2026

Just building your own microprocessor from gates is an easier way to learn about designing microcode and understanding how processors work(ed). But it can't hurt to study a few simple old designs like RISC or Transputer. The 80386 is on the other side of that spectrum, needlessly complicated because they wanted to be backwards compatible with an old bad design. There certainly is no need to go to university to learn chip design. Watching a few Alan Kay talks [3] or browsing Bitsavers computer designs [4] are good starting points. We made an easier way (than FPGA) to simulate and convert your gate level design into transistors on a chip (for less than $200 in 2026). We call it Morphle Logic [1]. Eventually you grow into making the largest fastest and cheapest supercomputer wafer scale integration [2]. [1] https://github.com/fiberhood/Morph

Read the rest

leLogic/blob/main/README_M... [2]https://www.youtube.com/watch?v=vbqKClBwFwI [3] https://www.youtube.com/watch?v=f1605Zmwek8 [4] http://bitsavers.informatik.uni-stuttgart.de/pdf/xerox/alto/...

In 80386 microcode disassembled

morphle·Apr 5, 2026

We make an asynchronous sea of gates runtime reconfigurable gate array chip very different from FPGA's but with the same use cases https://github.com/fiberhood/MorphleLogic/blob/main/README_M... The problem is you can make test chips like Aegis for around $10 (depending on the yield, on how many of the first 1000 chips actually work) but they are just that, test chips. In the case of Morphle Logic we make wafer scale integrations (WSI) with 10 billion transistors at 180nm for $750. That yields around 300 million 'gates', the largest commercial FPGA's barely get to 3 million. So our Morphle Logic WSI is the largest and fastest (up to 12 Ghz) FPGA you could get if we can find a few hundred buyers who want to pay up front (crowdfunding). Please email me if you are interested in such a enormous fast FPGA. I'll buy an Aegis FPGFA test chip jus

Read the rest

t to find out how hard it is to test a test chip. Good luck RossComputerGuy, I hope you get working chips back. The same fab and supplier lost our first taped-out chips in the mail... and then they went bankrupt.

In Aegis – open-source FPGA silicon

morphle·Feb 17, 2025

Without reading the article, I always quickly estimate what a DRAM based in-memory database would cost. You build a mesh network of FPGA PCBs with 12 x 12.5 Gbps links interconnecting them. Each $100 FPGA has 25 GB/s DDR3 or DDR2 controllers with up to 256 GB. DDR3 DIM have been less than $1 per GB for many years. 6.4x($100+256x4x$1)=$7,193.6 worst case pricing So this database would cost less than $8000 in DRAM chips hardware and can be searched/indexed in parallel in much less than a second. Now you can buy old DDR2 chips harvested from ewaste at less than $1 per GB, so this database could cost as low as $1000 including the labour for harvesting. You can make a wafer scale integration with SRAM that holds around 1 terabyte SRAM for $30K including mask set costs. This database would cost you $210.000. Note that SRAM is much faster than D

Read the rest

DR DRAM. You would need 15000/7 customers of this size database to cover the manufacturing of the wafers. I'm sure there are more than 2143 customers that would buy such a database. Please invest in my company, I need 450,000,000 up front to manufacture these 1 terabyte wafers in a single batch. We will sprinkle in the million core small reconfigurable processors[1] in between the terabyte SRAM for free. For the observant: we have around 50 trillion transistors[2] to play with on a 300mm wafer. Our secret sauce is a 2 transistor design making SRAM 5 times denser that Apple Silicon SRAM densities at 3nm on their M4. Actually we would not need reconfigurable processors, we would intersperse Morphle Logic in between the SRAM. Now you could reprogram the search logic to do video compression/decompression or encryption by reconfiguring the logic pattern[3]. Total search of each byte would be a few hundred nanoseconds. The IRAM paper from 1997 mentions 180nm. These wafers cost $750 today (including mask set and profit margin) and now you would need less than a million investment up front to start mass manufactoring. You just would need 3600 times the wafer amount compared to the latest 3nm transistor density on a wafer. [1] Intelligent RAM (IRAM): chips that remember and compute (1997) https://sci-hub.ru/10.1109/ISSCC.1997.585348 [2] Merik Voswinkel - Smalltalk and Self Hardware https://www.youtube.com/watch?v=vbqKClBwFwI&t=262s [3] Morphle Logic https://github.com/fiberhood/MorphleLogic/blob/main/README_M...

In Searchcode.com’s SQLite database is probably 6 terabytes bigger than yours

morphle·Nov 26, 2024

We also have been developing six kinds of reconfigurable processors (Morphle engine and SiliconSqueak) for our Wafer Scale Integration since 2008. A little information and slides can be found in the four hour talk [1] and in our papers since 2008 [2,3]. Our runtime reconfigurability comes from adaptive [5] load-balancing [1] JIT compilers (at runtime) that reconfigure hardware or generate hardware blocks at runtime with Morphle Logic [4]. We have 8-bit slices that you can combine per [block of] instructions into teams to make CPU or GPU or DSP or TPU cores and fine grained logic cells to make FPGA fabric and interconnect networks. Like Transmeta and Apple Silicon our processors also are optimized to emulate bytecode, Intel, ARM and RISC-V instructions. With large teams of 80 8-bit slices we can emulate Intel instruction blocks several ti

Read the rest

mes faster than high-end Xeon or AMD ZEN 4 cores can run them. [1] https://vimeo.com/731037615 [2] https://scholar.google.com/citations?user=mWS92YsAAAAJ&hl=en... [3] https://scholar.google.com/citations?user=6wa49gkAAAAJ&hl=en [4] https://github.com/fiberhood/MorphleLogic/blob/main/README_M... [5] https://youtu.be/CfYnzVxdwZE

In Ubitium is developing 'universal' processor combining CPU, GPU, DSP, and FPGA

morphle·Mar 20, 2024

Reconfigurable asynchronous logic automata: (RALA) https://dl.acm.org/doi/abs/10.1145/1707801.1706301 Morphle Logic https://github.com/fiberhood/MorphleLogic/blob/main/README_M... https://core.ac.uk/download/pdf/276277602.pdf With Google scholar you can search for 'asynchronous programmable logic' For example asynchronous logic with standard FPGA's https://www.researchgate.net/profile/Jerome-Quartana/publica... http://vlsi.csl.cornell.edu/~rajit/ps/fpga.pdf

In Unconventional Uses of FPGAs

morphle·Feb 5, 2024

>Attaching an MCU to an inverter isn’t exactly new technology No, its nothing special. Texas Instruments, Analog Devices and many others sell such chips for decades for several dollars each. What makes our chips (Microcontroller SoC) special is the $0,01 price and the high speed network between them so you can aggregate/balance/coordinate the inverter output voltage and the fully programmable inverter with all components in the chip except the inductor (a small coil). The bidirectional buck/boost is to charge/discharge battery cells individually, for solar cells we just need a unidirectional boost inverter. >8-core 64-bit MCU Sorry for the confusion, I could not edit my mistake. It is an single core 64 bit processor (ARM, X-86, Risc-V, bytecode and microcode) but reconfigurable to 8x8bit (for I/O processors like the RP2040 Raspberry pico)

Read the rest

, 4x16bit or 2x32bit or combinations like 4x8bit plus 1x32bit). The reconfiguration of the 8 bit slices is done with our special kind of FPGA fabric that we call Morphle Logic [1] >Do you have any technology that couldn’t be replicated? Only special physics knowledge. Our software. But nothing that they could not reverse engineer in a few weeks. >then any of the big players could have done it years ago Yes they could and they have. Their designs are pretty bad though, especially the microcontroller parts. And they just charge way too much for them. The Chinese companies that make the panels have not yet cloned their chips. >a negligible part of the overall cost. The price of the packaging, magnetics, testing Wrong. Our package is the cheapest with just two or 6 solder balls on the bare die, no package no pins. Testing, magnetics are no factor. >and integration into the panel will eclipse that No, the chips are in the place where the solar cell wires attach to each other already, the silicon sliver of material makes the standard wireing slightly cheaper. >claims of producing “30% more” energy also don’t hold up This is rounded estimated number from several science papers about maximum MPPT yield improvements and separately from wiring cells in parallel. Its certainly not my claim, to calculate this number scientifically you have to do this for every individual cell and panel on every different geographic location. [1] https://github.com/fiberhood/MorphleLogic/blob/main/README_M...

In Oxford PV sets new solar panel efficiency world record

morphle·Jan 7, 2023

That depends. If you would use our asynchronous runtime reconfigurable array called Morphle Logic [1] instead of FPGA (Field Programmable Gate Array), you could program this hardware Twitter in a 1000 hours and have it run at 50 Tbps. You would not need to know much about hardware but you would get a thousandfold speedup of your software. [1] https://github.com/fiberhood/MorphleLogic/blob/main/README_M...

In Production Twitter on one machine? 100Gbps NICs and NVMe are fast

morphle·Jan 7, 2023

We have designed several versions of Morphle Logic asynchronous runtime reconfigurable arrays. They can do the same as FPGA's but are not exactly the same gate arrays, as explaind in this readme: https://github.com/fiberhood/MorphleLogic/blob/main/README_M... You can add Morphle Logic to any processor including RISC-V and program/reconfigure the gate array by just writing SRAM. So you can reprogram small parts in nanoseconds if you want, even while the circuit is running! We've added a small RISC-V processor to make it easy to reprogram the Morphle Logic. There is a small caveat: you can not buy our chips yet... I need $100K and 3 months to tape out new chips first. An equivalent Morphle Logic of a small FPGA like the ICE40 would cost half a dollar, the equivalent of an Virtex Ultrascale would cost around $600. Some parts of these reconfi

Read the rest

gurable arrays could run at 12 Ghz. Email us at morphle [at] ziggo { dot} nl

In Self-Modifying FPGAs?

jecel·May 21, 2021

There have been FPGAs in the past which used the logic blocks for routing, including the Xilinx 6200. I think that was also the case for the Atmel AT40K FPGAs, but could be remembering wrong. In fact, our project for the previous Google shuttle was an FPGA-like device which also routes data using logic cells. Here is an introduction to the idea: https://github.com/fiberhood/MorphleLogic/blob/main/README_M... It worked in simulation and the chip is currently scheduled to be shipped to us on September 6. There were 2 or 3 projects that were more conventional FPGAs.

In Chip Ignite: Rapid IC Creation