skywater-pdk

We did back in 2007: https://en.wikipedia.org/wiki/Open_Graphics_Project And there have been some others as well: https://en.wikipedia.org/wiki/Free_and_open-source_graphics_... Recently https://www.furygpu.com/ Part of the problem is that every ASIC manufacturer (and indeed each fabrication process) has a different toolchain with a different set of primitives for circuit design. Yosys and other open tooling for FPGAs has helped a great deal in lowering the barrier to chip design and by association reuse of circuits. But every ASIC, at the moment, is tied to some vendor's PDK. Here's the one Google open sourced for Cypress Semi's SKY130 process node: https://github.com/google/skywater-pdk

SkyWater's 130nm has been used for all (most?) of the Efabless × Google MPW (multi project wafer) runs. That PDK was open sourced as part of that initial effort. https://www.skywatertechnology.com/first-google-sponsored-mp... https://github.com/google/skywater-pdk There's a bunch of other PDKs running around now too. But progress does seem to have distinctly tapered off.

Google have a foss prouction flow for 130nm https://github.com/google/skywater-pdk?tab=readme-ov-file You have to know a lot before you can know what you're looking at.

Is there a open source simple CPU? Preferably Intel compatible or able to run Linux? Something I can build in my garage or in a simple microprocessor fab. https://github.com/google/skywater-pdk

It looks neat, but the process node is 1 um with 3 metal layers. The open Skywater PDK is 130 nm : https://github.com/google/skywater-pdk (though I don't know how reliable the PDK is?)

From working in a somewhat related discipline, the PDKs for the high end nodes (think tsmc N16 and lower) are quite hard to obtain and require your org to pass security audit. In addition to that the cadence licenses are priced very much for a big-org rather than a startup. Does your chip absolutely need a modern node? I'm assuming you've seen the open source skywater pdk, but here it is just in case. https://github.com/google/skywater-pdk

That would be really neat, but I haven't seen anyone even make a CMOS imager on SKY130. https://github.com/google/skywater-pdk One could make an array of thermopiles, like the hacker that made their own imager out of discrete diodes (digiOBSCURA) . But each pixel would cost $7. https://www.digikey.com/en/products/detail/excelitas-technol... One might be able to make an array of thermistors (possibly with active cooling using a peltier) like the diycamera (digiOBSCURA) below. Might be an application of combining many RC oscillators in a tree and recovering the signal with an FFT. I have a gut feeling this is possible, but haven't show it. Isn't this the same as or similar to your keyboard multiplexer design? https://www.digikey.com/en/products/detail/panasonic-electro... https://github.com/IdleHandsProject/diycamera (digiOBSCURA) One could

Taping out an actual chip inevitably involves IP that's not yours, e.g. the standard cell library and other 'physical' IP like memories and flash. You cannot open source that as it is not yours and in general the owners of it won't want to open source it either (though there are exceptions e.g. the Skywater 130nm PDK https://github.com/google/skywater-pdk). In OpenTitan we've built all the 'logical' IP ourselves from the ground up. This is the Verilog RTL you can see in our repository but you need the 'physical' IP to make a real chip. We haven't built any physical IP so we need to get it from the traditional industry sources which means traditional industry licensing (i.e. very much not open).

Pretty neat, a python tool that converts Verilog to an IC layout so that you can make your own custom SOC (assuming you have a substantial budget to pay for fab). Since it's not clearly stated on the front page, I had to go digging to figure out what processes it supports. Looks like FreePDK45, which is "an open-source generic process design kit (PDK) (i.e., does not correspond to any real process and cannot be fabricated)" [0], ASAP7 "Warning Work in progress (not ready for use)" [1] and Skywater130 which "As of May 2020, this repository is targeting the SKY130 process node. If the SKY130 process node release is successful then in the future more advanced technology nodes may become available." [2] The floorplanner supports their ZeroSOC [3] which I guess is based on TitanSOC [4] If this sounds negative, it's not, I just couldn't figure

So I would say to that extent they do, the foundries provide dev kits with cells to use on their process, and there's definitely the same incentive, good reusable IP gets you products faster which gets them more business. I think a lot of the landscape is just driven by the sheer cost of getting it wrong. Spinning a pcb is a bummer. Needing a new mask set is so much worse. There is eFabless, among other efforts in the vein you describe, they do a multi project wafer shuttle thing that google sponsors using skywater. It's supposedly an open source PDK, I haven't used it. https://github.com/google/skywater-pdk

"As should be obvious by now, there is no situation where these foundry processes and tools are open source." This is already false. The famous OpenPDK by Skywater (sponsored by Google) is proving this article wrong from the beginning. (https://github.com/google/skywater-pdk) Yes, thats a rather old technology node, but you can now synthesize your free RISC-V design with a free Toolchain (openROAD) onto this open PDK. Amazing times!

This one has an ESP32 and also 8 analog input pins, a weak point of the RP2040's thus far. Raspberry Pi took advantage of the Google 130nm process: https://github.com/google/skywater-pdk, and came up with a visionary device. Sadly no RISC-V.

The commercial tools are indeed very expensive but the required data files can be as much of a problem. Normally you have to sign a bunch of NDAs (non disclosure agreements) to get your hands on the design rules and standard cell libraries supplied by the foundries and required to make the tools work. One effort to organize several previously available open source tools into a practical system is OpenLane, which is based on the DARPA OpenRoad project: https://woset-workshop.github.io/PDFs/2020/a21.pdf Recently, Google has financed a project where a foundry has made its data files available without any NDAs: https://github.com/google/skywater-pdk The combination has made it possible to have completely open source chip designs.

> Also, the caravel requirement has been known for at least three months. That is simply false. Maybe known to insiders at eFabless. Seriously where do you see any public mention of "caravel" three months ago? There's absolutely nothing about it on the mailing lists [1] [2]. > it was announced at the start of the program Where? I heard about this in late July and have been following this very closely since they posted the design rules in early September. I've probably read through the DRC rule document more closely than anybody outside of Google/Skywater/eFabless. Two weeks ago there was nothing anywhere in any of that about having to use their "Caravel" management padframe. As of 15-Sep (git commit 107103f922db43408f59a1540cd4bd3737b30172) the text "caravel" does not appear anywhere in the PDK [3]. I checked with: $ find . -not

I have no context into your background knowledge, but I'll assume you know how to write some software. Coming from a software background, my recommendation would be to come from above and work down towards the chips. The perfect route to take is to work with a soft RISC-V cpu running on an FPGA with a totally open toolchain. By utilizing open tools, you have the agency to both modify the tools for your own use, gaining knowledge into how the tools work as well as participating in the technology graph. As soon as you add even a minor feature to the tooling, you then have the ability to add features for other people. This makes you valuable and will open other opportunities. Get a Lattice FPGA supported by Yosys [1] and learn Chisel [2] and Verilog [3] while working through Nand To Tetris [4] Once you understand the hardware enough, those