skywater-pdk

> Also, the caravel requirement has been known for at least three months. That is simply false. Maybe known to insiders at eFabless. Seriously where do you see any public mention of "caravel" three months ago? There's absolutely nothing about it on the mailing lists [1] [2]. > it was announced at the start of the program Where? I heard about this in late July and have been following this very closely since they posted the design rules in early September. I've probably read through the DRC rule document more closely than anybody outside of Google/Skywater/eFabless. Two weeks ago there was nothing anywhere in any of that about having to use their "Caravel" management padframe. As of 15-Sep (git commit 107103f922db43408f59a1540cd4bd3737b30172) the text "caravel" does not appear anywhere in the PDK [3]. I checked with: $ find . -not

I have no context into your background knowledge, but I'll assume you know how to write some software. Coming from a software background, my recommendation would be to come from above and work down towards the chips. The perfect route to take is to work with a soft RISC-V cpu running on an FPGA with a totally open toolchain. By utilizing open tools, you have the agency to both modify the tools for your own use, gaining knowledge into how the tools work as well as participating in the technology graph. As soon as you add even a minor feature to the tooling, you then have the ability to add features for other people. This makes you valuable and will open other opportunities. Get a Lattice FPGA supported by Yosys [1] and learn Chisel [2] and Verilog [3] while working through Nand To Tetris [4] Once you understand the hardware enough, those