Digital

I'm not the author of the post itself, but the 74181 chip seems to be defined in the simulator: https://github.com/hneemann/Digital/blob/master/src/main/dig...

Theres the open source Digital (https://github.com/hneemann/Digital) which can run simulations but then export Verilog. If you have an ICE40 based GPU then in theory you can then use open source tools (like apio) to get that onto your FPGA. I've seen some impressive fpga tasks being generated by that. I'm early in my learning of FPGA and have done nandgame and some other non-HDL circuit learnings. I have gone back and forth if I want to design my project via HDL or via something like Digital. There's not an easy pro/con either way. For example, everything I've read is that the verilog block diagram tools kinda create isn't behavior, which makes optimization by FPGA compilers hard, because it can't automatically infer optimal feature gate usage if you are giving transistor level HDL vs behavior HDL. Likewise, it's not totally clear if

Tried it on Windows 11 but got a Java run time error. Used the recommended JRT https://adoptium.net/ Wandered through the https://github.com/hneemann/Digital site and saw past issues with JRT but no obvious solution. I have a couple hundred GALs of same or similar model number of new old stock and was hoping to somehow make use of them.

This is a tangent, but in the first question post the OP mentions considering implementing helper circuitry with quote "a GAL16V8 or something but I don't think I understand them well enough, programmers are very expensive and the programming software is closed source & Windows-only as far as I know." I went down this path on a project a few years ago and I just wanted to point out that you can burn the fuse file for the Lattice GAL16v8 or GAL22v10 chips these days using a cheap TL866 Plus programmer... And there is a very cool way to write the JEDEC fuse files- you can draw out the circuitry you want using the [0] Digital simulation package (it is similar to Logisim) and export a compatible bitstream to burn from there. Thus skipping the need to find a way to run the old WinCUPL or the even older DOS program that was used to do the syn

I'm more curious if there is something that makes visualizing the Verilog easier... for instance, I've done some small projects where I used Digital [0] (which is so unfortunately named, but awesome) to put blocks of Verilog into the visual representation and then connect my blocks together (like ALU, block ram, registers etc) and run simulation. But the problem is taking all that out back to Verilog and then doing my synthesis with Yosys is a manual chore. I am wondering if there is some sorta... IDE that is letting people inspect projects with lots in individual Verilog files quickly and show the structure visually (and manage test benches run Icarus and GTK wave etc). I haven't seen this outside of vendor-specific tools like Xylinx's Vivado and I'm wondering if I am just missing something or if that kinda of IDE doesn't exist in any

Logism is still a great program although it requires an old Java runtime environment, 1.5.0. Many schools still seem to use it however (development ended in 2014). Perhaps its descendant is Digital? https://github.com/hneemann/Digital

I have been building a CPU using: https://github.com/hneemann/Digital Much faster than Logisim, UI a little clunky, but my CPU runs around 0.5Mhz and it has very nice peripherals like Telnet, graphics ram, VGA etc Terrible name that is hard to google, but great tool.

This is a game. Should you want a digital logic simulator that's not a game, check out https://github.com/hneemann/Digital.

Well logisim is dead, but evolution is a fork and then there's Digital https://github.com/hneemann/Digital which is I think a reimplementation of Logism's concepts? I also hand designed a custom 16 bit CPU in logisim, because I was struggling to understand Nand2Tetris's HDL as well as I liked, and also because I stopped following the curriculum to go my own way. Logisim has a few hang ups, starting with a rather low upper bound on clock speed, completely single threaded simulation, and no process for PLL or similar clock multiplying strategies so if you want to do internal processor management or microcode based implementations, you will be stuck with an even lower fraction of that clock speed. The UI is slightly clunky by modern standards, debugging complicated circuits is less than fun, and the file format is less than great if you want

This one is written in Java: https://github.com/hneemann/Digital You can export your project as a Verilog file that can be used in the various FPGA tools.

> Maybe it'd be possible to write an integration for the (unmaintained) Logisim to export the schematic to a HDL of some sort to get close. No need, Digital (https://github.com/hneemann/Digital) already does this: > A circuit can be exported to VHDL or Verilog. There is also direct support for the BASYS3 Board and the TinyFPGA BX board. See the documentation for details. The examples folder contains a variant of the example CPU, which runs on a BASYS3 board.