STstuartjohnson12·Dec 15, 2025
In Show HN: Sub-microsecond (890 ns) trading execution research systemkrish567366
submicro-execution-engine
C++2025–2025
krish567366 / submicro-execution-engine
submicro-execution-engine
Sub-microsecond bare-metal execution engine with deterministic replay, lock-free order path, and hardware-timestamped latency measurement.
2Distinct people
2Mentions
0Explicit recommenders
105GitHub stars
What to know before exploring
What it is
Sub-microsecond bare-metal execution engine with deterministic replay, lock-free order path, and hardware-timestamped latency measurement.
GitHub
Where it is used
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This week on Hacker News
Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 1:49:46 PM UTC.
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Mentions over time
HN mentions by hour2 dated mentions
Observed mentions: 2025-12-15 14:30:15 UTC to 2025-12-15 16:45:42 UTC.
Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.
View mention counts and date ranges
| Period | Start (UTC) | End (exclusive, UTC) | Mentions | Submissions | Comments |
|---|---|---|---|---|---|
| Dec 15, 14:00 | 2025-12-15 14:00:00 UTC | 2025-12-15 15:00:00 UTC | 1 | 1 | 0 |
| Dec 15, 15:00 | 2025-12-15 15:00:00 UTC | 2025-12-15 16:00:00 UTC | 0 | 0 | 0 |
| Dec 15, 16:00 | 2025-12-15 16:00:00 UTC | 2025-12-15 17:00:00 UTC | 1 | 0 | 1 |
What Hacker News says
2 sourcesShow HN: Sub-microsecond (890 ns) trading execution research system
I am sharing a research-grade, open-source trading execution framework that achieves a median end-to-end decision latency of 890 nanoseconds on commodity hardware.
The project is designed for education, systems research, and latency instrumentation, not for live trading. It focuses on understanding exactly where every nanosecond goes in a trading execution path.
Key features:
- Kernel-bypass networking: Direct userspace access to NICs via custom drivers, 20-50 ns RX latency
- Lock-free SPSC/MPSC queues: Zero-copy architecture
- SIMD feature extraction: About 40 ns per update using AVX-512
- Deterministic replay: Bit-identical execution paths, SHA-256 verified
- Nanosecond-level metrics: Full audit logs and performance dashboard
Technical stack: C++17 and Rust, NUMA-aware memory allocation, cache-line alignment, inline assembly for hot pat
Read the rest
hs.
The framework is modular, allowing experimentation with different NIC drivers, feature extraction pipelines, or order-flow models such as Hawkes processes or Avellaneda-Stoikov logic. Everything is open source and documented.
Links:
Live demo: https://submicro.krishnabajpai.me/
Source code: https://github.com/krish567366/submicro-execution-engine
Bare-metal NIC drivers: https://baremetalnic.krishnabajpai.me/
I would welcome feedback from anyone working on low-latency systems, networking, or HFT research.
Some questions for discussion:
- Which part of the execution path is typically hardest to optimize?
- What measurement techniques do you trust for sub-microsecond systems?
This project is for research and educational purposes only. It does not connect to exchanges or execute real trades. It is intended as a sandbox for understanding ultra-low-latency execution.
I am happy to answer questions about methodology, performance, or design trade-offs.