circt

Does it work better when using compiler based ecosystem (e.g. https://github.com/llvm/circt)

Basically no. Almost everybody uses SystemVerilog. The main issue is that all the simulators only support SystemVerilog so every other HDL is compile-to-SV, and often they output truly awful code that is a nightmare to debug. Also SV has an absolutely enormous feature set, and often alternative HDLs miss out important parts like support for verification, coverage, formal verification, etc. Getting away from SV is like getting away from JavaScript. The network effects are insane. There was an attempt to make a kind of IR for RTL that would break the tie with SV (kind of like WASM has for JS)... I can't remember the name (LL..something?) but it seemed to have died. Maybe this is similar I'm not sure: https://github.com/llvm/circt Anyway the only really interesting new HDL I've seen is https://filamenthdl.com/

This is not strictly true anymore as the low-level (FIRRTL) compilation is powered by CIRCT (http://GitHub.com/llvm/circt) which is built using MLIR (part of the LLVM project: https://GitHub.com/llvm/llvm-project)

MLIR (https://mlir.llvm.org/) is a quickly growing compiler toolkit which attempts to synthesize the learnings of LLVM and currently powers compilers for programming languages, machine learning and circuit design (https://github.com/llvm/circt). and there are a ton of companies with real employees working on it (including Microsoft) and MLIR is at the core of Chris Lattner’s new company, ModularAI. I’d recommend taking a look at it, there are a large number of ways to get involved and a number of paths from contributor to employee.

> At best you can do the same with one reduced canonical simplified verilog source-to-source translation. Parsing Verilog and generating valid Verilog is fairly difficult. If you want to stay with Verilog, the most realistic alternative to firrtl right now is the RTL-IL representation used inside of yosys. > at worst it does not do the primary function of "being" IR for RTL, because it should've been a graph, not another language with simplified syntax. Canonicalized LoFirrtl (i.e., the representation the compiler lowers Chisel to) is essentially SSA (single static assignment) which encodes a dataflow DAG. So on a per module level, firrtl does represent the circuit as a graph. What you might be talking about is the fact that this graph isn't global. Having a global circuit graph could make some analyses easier, but it might require essent

Did you see the work being done on CIRCT? https://github.com/llvm/circt I remember one of the reasons you did not want to use firrtl was that its compiler is implemented in Scala and thus hard to integrate into other projexts. CIRCT will solve that problem by providing a firrtl compiler implemented in C++. Other languages like Verilog/VHDL and new high level languages for HLS-like designs are also on the todo list.

Call me skeptical but to claim 1000x improvement for circuit simulation is at least hyperbole or outright lying. I will love to be proven wrong though. This by the fact that Julia is still depending on third party numerical libraries, e.g. OpenBLAS that depends on faster numerical languages like Fortran. If you want to see next generation circuit simulation and automation that already working check out JITX. The simulator is using their advanced LB Stanza language which similar if not better than Julia[1]. This is the same team from Berkeley that proposed CHISEL and FIRRTL. Other promising efforts on next generation digital and analog circuit design are from MLIR by LLVM team and LLHD from ETH Zurich [2][3]. [1]http://lbstanza.org/ [2]https://github.com/llvm/circt [3]http://llhd.io/

> I thought Berkeley's BOOM is way more advanced implementation of RISCV than VexRiscV and it is written in Chisel3. It is a lot more advanced and thus harder to get started with than VexRiscV. > BOOM does not look like most effective in terms of LUTs utilisation core. So the problem is also that the BOOM design is targeted at ASICs. The developers do not generally synthesize BOOM for FPGA. Only as a FireSim project which is using FPGAs to do fast simulations in order to get more accurate performance figures by running real world benchmarks (multiple MHz of target frequency). None of the developers are interested in using BOOM as a computer on an FPGA and thus no one has provided support for that. > Another thing I also disliked in Chisel3 is dependancy on new intermediate representation of hardware (FIRRTL) which adds one more layer of a

Neither Xilinx nor Intel are in the business of making simulators (and in both cases, it shows). If there is an opportunity to graft the LLVM model into the FPGA world, IMO it's the simulators. Unfortunately it requires some creativity to support encrypted RTL in an open-source simulator, and both vendors require a way to supply simulation models without exposing source code. Doubly unfortunately, the open-source simulators are all language-specific and any attempts to bridge the gap have been only limited experiments. A brand-new simulator architecture seems necessary but has its oxygen starved by the rest of the ecosystem, open-source and commercial. I am watching https://github.com/llvm/circt with interest but I don't think this is quite focused on simulators the way I think is necessary.