ibex

> Yes, there is one in the proposed "B" extension. Not good enough: it won't be in the smaller chips, or even in the biggest ones for a good while. The lowRISC Ibex core which I work on and whilst not the smallest core is definitely at the small end has full bitmanip extension support: https://github.com/lowrisc/ibex Yes the extension isn't finalised yet but we're not expecting much change so we can tweak the implementation to match the ratified standard when it appears. I'd also note bitmanip is broken up into subgroups so it's possible smaller cores will only implement the simple stuff (e.g. Popcount) to avoid the overhead of the full implementation.

We need a better list, but it would be quite some work to make it. I'd like a list of performance, size, implementation language and bus interfaces. I've been looking at this one for high end (1.9 DMIPS/MHz!): https://github.com/ultraembedded/biriscv Google/lowRISC has this one: https://github.com/lowRISC/ibex I'm using picorv32 right now on Lattice ECP5- running code out of SPI-flash, but I added an instruction cache for speed. It's amazing how many RISC-V things are happening all at once right now. Anybody know of any free RISC-Vs with floating point? It would be helpful to have something similar to ARM Cortex-M4F. Edit: From the "riscv-cores-list" I see WARP-V, which I'm not interested in due to "TL-Verilog". But its FPU is this: http://www.jhauser.us/arithmetic/HardFloat.html So all of these RISC-Vs should have optional FPU support

I'm slightly surprised the author didn't mention the core I work on Ibex: https://github.com/lowRISC/ibex but maybe not too surprised as it's primary target isn't FPGA softcore, though it does work fine for this purpose. It's got an extensive verification environment (though relies on UVM so you need closed tools to run it, we have a verilator setup for running RISC-V compliance and arbitrary binaries), good documentation and we're pushing the performance up (you can get 3.09 CoreMark/MHz with the current master and that will increase with some branch prediction work I'm currently doing). It's configurable so you can choose your own trade offs between size and performance. Plus we've got support for the B (bitmanip) extension, which our verification environment also tests. All cores have their pros and cons and Ibex is no exception but if

It depends what you want to do? Do you want to build a processor from scratch? A basic processor for core RISC-V is actually quite simple. The RISC-V I specification (all the core instructions not including multi/div, none of the privileged spec) is not complex. Implementing something like the story talks about is obviously far more complex. If you're mostly interested in putting together existing processors that can again can vary in complexity, there are some things with 'batteries included' where you can just spin up an FPGA image that works then go poking around, others where there will be significant work in integrating things into a working system. I'll give a plug to Ibex (https://github.com/lowRISC/ibex) which is the core I work on, it doesn't have an MMU and is targetted at embedded applications. It's a 'real' core, in that it's