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lowRISC
ibex
SystemVerilog2019–2026
lowRISC / ibex

ibex

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

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11Distinct people
16Mentions
0Explicit recommenders
2.2KGitHub stars
REPOSITORY AT A GLANCE

What to know before exploring

What it is

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

GitHub

Where it is used

No documented product use was verified in the last source check.

What people are saying

No recommendation phrase was found in the indexed comments.

No classified warning is attached to this page. Read the discussions before treating silence as approval.

Also in these discussions

No other repository is repeatedly linked in the same discussions.

This week on Hacker News

Nov 8–Nov 15 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/15/2026, 7:24:48 PM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by year16 dated mentions

Observed mentions: 2019-11-05 18:59:53 UTC to 2026-06-14 18:23:41 UTC.

012342019-01-01 00:00:00 UTC to 2020-01-01 00:00:00 UTC (exclusive): 1 mentions; 1 submissions, 0 comments20192020-01-01 00:00:00 UTC to 2021-01-01 00:00:00 UTC (exclusive): 4 mentions; 0 submissions, 4 comments2021-01-01 00:00:00 UTC to 2022-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2022-01-01 00:00:00 UTC to 2023-01-01 00:00:00 UTC (exclusive): 3 mentions; 0 submissions, 3 comments20222023-01-01 00:00:00 UTC to 2024-01-01 00:00:00 UTC (exclusive): 3 mentions; 0 submissions, 3 comments2024-01-01 00:00:00 UTC to 2025-01-01 00:00:00 UTC (exclusive): 3 mentions; 0 submissions, 3 comments2025-01-01 00:00:00 UTC to 2026-01-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 comments2026-01-01 00:00:00 UTC to 2027-01-01 00:00:00 UTC (exclusive): 1 mentions; 1 submissions, 0 comments. Incomplete calendar period.2026*

* An incomplete calendar period is marked with an outlined bar. Its count is not directly comparable with a full period.

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

View mention counts and date ranges
UTC ranges include their start and exclude their end. Select a period to filter the source evidence.
PeriodStart (UTC)End (exclusive, UTC)MentionsSubmissionsComments
20192019-01-01 00:00:00 UTC2020-01-01 00:00:00 UTC110
20202020-01-01 00:00:00 UTC2021-01-01 00:00:00 UTC404
20212021-01-01 00:00:00 UTC2022-01-01 00:00:00 UTC000
20222022-01-01 00:00:00 UTC2023-01-01 00:00:00 UTC303
20232023-01-01 00:00:00 UTC2024-01-01 00:00:00 UTC303
20242024-01-01 00:00:00 UTC2025-01-01 00:00:00 UTC303
20252025-01-01 00:00:00 UTC2026-01-01 00:00:00 UTC101
2026 (partial)2026-01-01 00:00:00 UTC2027-01-01 00:00:00 UTC110

What Hacker News says

3 sources
taway32r41·Sep 6, 2023
I definitely agree with the primary point, "building a chip that meets specfic requirements we got from the customer" is not easy and is what matters. However, RISCV cores abound. In pretty much any HDL known to man with varying design trade-offs and capabilities. It's extremely difficult to differentiate at the RTL level at this time. Not impossible, but it would be a significant investment, which is I guess SiFive's business model. Sell IP at prices cheaper than that. Here is a high quality, well documented, SystemVerilog version intended for embedded applications that I know has been included in multiple ASIC and FPGA designs successfully. https://github.com/lowRISC/ibex
In SiFive’s P870 Takes RISC-V Further
panick21_·Mar 26, 2023
Of course these things never die, MIPS wont die. ARM wont die. Nobody is claiming they will. But also, you don't start very many a huge amount of new project with 8052s. Performance isn't that important maybe (depends on the application), but energy often is, size is, having lots of vendors is, having a large software base is. > So I'm really not sure how or why RISC-V would break into the uC world / low end. If by lower end you mean 8-bit, then no it wont. But one of the large adopters of RISC-V are actually places where there used to be tiny 8-bit cores and now people want more substantial 32-bit cores and RISC-V is really good there. And it has already broken into that market as there are already lots of RISC-V products shipping, lots of them in lots of consumer electronics from China. RISC-V will continue to grow in that market, if yo
Read the rest
u were a MIPS costumer for example, you are likely gone move on to RISC-V? > If anywhere, they have a chance at the higher level, like at Rasp Pi level chips or stronger. At the very low end being very cheap, not involving as many lawyers actually matters quite a bit because volumes are high. Specially when there are very competitive verified opensource cores as well. Ibex: https://github.com/lowRISC/ibex Used by Google in the OpenTitan Project Open Hardware Group: https://www.openhwgroup.org/ Chips Alliance: https://www.chipsalliance.org Not to mention all the commercial offerings (or commercial offerings that support those open-cores). They might not be open, but its easy to get up and running with RISC-V compared to commercial stuff. There is just so much education moving to RISC-V. Lots of people will be educated in RISC-V and lots of people will look at some of these OpenSource cores to learn. When places like Berkley, Stanford and ETH embrace something it usually trickles down to most universities.
In Arm wants to charge dramatically more for chip licenses

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