swizzle-inventor

Except that, for CUDA, they do. https://github.com/NervanaSystems/maxas exhibited significantly higher performance than Nvidia's own SGEMM kernel, and https://github.com/mangpo/swizzle-inventor beats all named competitors in the non-texture-memory-input-using implemention. Namely, NVIDIA Performance Primitives, ArrayFire, and Iandola et al ( https://doi.org/10.1109/ICIP.2013.6738436 ). As for GC implementations: did you consider ZGC in that statement? It's GPL 2.

Hi, this looks like a strong result. Congratulations! Short answer: to scale up hardware synthesis, it may be necessary to change the encoding rather than look for a better solver. More details: I should first say that I have limited experience with synthesizing hardware. My lessons come from [1], where synthesized a small Wallace Tree multiplier. What that taught me is that hardware arithmetic circuits should perhaps not be formulated as a 2QBF problem -- because you might need too many counterexample inputs to terminate the CEGIS loop. Instead, I believe that the circuit synthesis should use algebraic reasoning (for correctness) and combinatorial reasoning to explore the space of candidate circuits. Since one symbolic input is sufficient to show correctness, the problem simplifies from 2QBF to SAT. This idea is briefly explained in S