mv-ddr-marvell

Wow, I was spoiled building firmware for my ARM boards then (building, not developing). Marvell has a source available DDR driver that actually takes care of training on a few of their platforms! https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell

Marvell/Armada CN9130 SoC ... public-but-non-upstream code for uboot Dude, not even close. That repo is for an opaque blob: https://github.com/SolidRun/cn913x_build/blob/master/binarie... ... which is mashed together-bits of other blobs, including the notorious will-never-be-open-source highly-radioactive "snps blob": https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/... and its vile EULA which you have agreed to: https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/... That shit contains an ARC core. Never heard of ARC? That's okay, most people haven't. It's an obscure niche architecture used for almost nothing except for ... drum roll ... the Intel Management Engine (up until 2019). Gee I wonder why that's in there. Don't touch Marvell shit with a ten foot pole, it's blobs all the way down. They're just good at h

Its commendable, but if you look closely https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/... its not all "open". I think there is a fair amount of discussion about whether poking a bunch of random values into random registers is "open".

Marvell has their DDR3+4 initialization straight on GitHub: https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell (even this includes a Synopsys blob for the PHY, but only on some platforms — no blobs on A70x0/A80x0 thankfully) It's really stupid that other vendors can't just do the same.

> requires some care when selecting your gear Doesn't that mostly boil down to "avoid anything newer than Ivy Bridge/Bulldozer"? > high performance memory […] controller function blocks There are DDR4 controllers with FOSS training code out there :) https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/...