xv6-d1

Comer was also my introduction to OS design and I still like the approach used in his Xinu books. I had a quick glance at the OS in the linked article. This seems to be based on a 32-bit RISC-V with MMU. However, AFAIK, all available RISC-V SoCs with MMU are 64-bit. The 32-bit cores are only used for embedded controllers (unless you want to start designing an FPGA-based system). The 32 and 64 bit versions of RISC-V are _not_ binary compatible, but the differences are rather small. Porting the MMU code from 64 to 32 bit or the other way round is not very complex, see my RV32 port of xv6 at https://github.com/michaelengel/xv6-rv32 (the regular MIT xv6 version only supports RV64). The major difference is that virtual address translation on RV32, sv32, uses a two-level page table (10 bit index for the first level, 10 bit index for the second

The x86 version of xv6 is no longer updated, the last updates took place about 7 years ago. Current xv6 supports RISC V in qemu, there are also ports to real RISC V devices (Kendryte/Canaan K210 by Huazhong University of Science and Technology, Allwinner D1 and StarFive JH7110 by me) and FPGA implementations (by Michael Schröder). https://github.com/mit-pdos/xv6-riscv/ (qemu) https://github.com/HUST-OS/xv6-k210 (K210) https://github.com/michaelengel/xv6-d1 (Allwinner D1) https://github.com/michaelengel/xv6-vf2 (JH7110) https://gitlab.com/x653/xv6-riscv-fpga (RV32 FPGA)