cheriot-ibex

> Security through Obscurity still reigns. That's not the case at all. The spec is developed in the open: https://riscv.github.io/riscv-cheri/ If you want to run CHERI code, it's true that silicon isn't easily available, but that's simply because it takes time. Various companies are working on it (Codasip, SCI, Secqai, lowRISC, etc.). But you don't need silicon to run CHERI code. There are various emulators available that support it. There's QEMU: https://github.com/CHERI-Alliance/qemu There's also the RISC-V Sail model, this is the latest CHERI branch: https://github.com/CHERI-Alliance/sail-riscv (unfortunately it is a bit behind upstream master, and also a bit behind the latest CHERI spec which is still evolving). There are also a few open source chips available that implement CHERI which you can run in Verilator or an FPGA. For example