slang

As a software developer who later got into hardware design, I've always been pretty disappointed with the quality of HDL tools. You get a bit spoiled by the quality of compilers like gcc and clang, and then you run into ridiculously expensive closed-source SystemVerilog compilers that fall apart on valid and obvious code, can't be run in a build farm, and which report cryptic messages for errors. So I've been working on my own open source SystemVerilog compiler / frontend for a while now, and it's nearing 100% completion in terms of language support. https://github.com/MikePopoloski/slang

yosys [1] is the the open-source synthesis tool and also supports formal verification and other analysis. however, it's Verilog front-end is basically Verilog-2005 with a hodge-podge of newer features added on but it is unfortunately very buggy and incomplete. Mike Poploski's slang [2] is an absolutely top-notch System Verilog parser and elaborator that already supports nearly all System-Verilog 2023 features already. why not adapt the slang front-end to yosys so we can have a proper modern System Verilog HDL entry with yosys's excellent synthesis and analysis engines? Martin Povišer just did it! Thank you Martin. [1] https://github.com/YosysHQ/yosys [2] https://github.com/MikePopoloski/slang

Going to plug my work on this here: https://github.com/MikePopoloski/slang At some point I'd like to see it integrated as the frontend to tools like Yosys to get best-in-class SystemVerilog support in open tools.

Somewhere on my todo list is to make a systemverilog autoformatter using the parser from slang [1]. [1]: https://github.com/MikePopoloski/slang