Bitgrid

Bitgrid[1][2] is a continuation of an idea I've been carrying around since the 1980s, and tweaking from time to time. If I can maintain focus long enough, I intend to learn RTL, VHDL or Verilog well enough to get it entered in one of the Google open source chip shuttles. I think this approach to computing if applied to neural networks may offer a cheap way to get far more compute, perhaps exaflop performance out of a single chip. It's an FPGA without routing hardware, which on the face of it, is the stupidest thing to do. However, because of the clocked nature of the bitgrid, you all data only has to travel to neighboring cells, so lines will be short, and clock rates should be able to be up in the gigahertz range. Instead of worrying about how quickly you can get a signal from one side of the chip to the other, the latency will be 1/2 of

>explore alternative and novel avenues for computing Ok... lemme take you down a rabbit hole.... imagine an FPGA, but with no routing hardware what so ever... just a vast sea of LUT (Look Up Tables) base cells with 4 bits of input and output, from each of its neighbors. A latch on the inputs is clocked like a chessboard... all of the white, then all of the black... this slows down processing, but completely removes timing issues. Properly programmed, a large fraction of all the LUTs could be doing computation on every clock cycle. Imagine a 1024x1024 grid of these.... you could throw inputs in one side of the array, and get outputs every clock cycle, as everything is pipelined. Programming.... no coherent ideas about that... I have some, involving working backwards from the output. Lets assume 1024x1024, 100 Mhz clocking, and a FP16 takin

One of my bucket list items is to bring about a new model of computation, the BitGrid[1]. It's a cross between a systolic array and FPGAs... but it would definitely NOT work as a practical FPGA. On the other hand, maybe it could bring Exaflop computing to the masses? A million LUTs all working in parallel is a ton of horsepower. And it should only be a bit bigger than a 2 megabyte Static RAM [1] https://github.com/mikewarot/Bitgrid/blob/master/WhyBitGrid....

I was working on a BitGrid simulator[1], but I got stuck. I got the emulation running, and at a reasonable speed too. (I can emulate a 1024x1024 bitgrid at 34 Hz on my desktop machine). I'm stumped as to how I should do I/O. The primary aspect of the bitgrid is that it's an FPGA with zero routing fabric, but clocked to prevent race conditions. This means that results could be skewed. I could either force the outputs in parallel before output, or have the output handler deskew them externally. It's silly that I'm stumped at this point. If this idea actually works, you could get Exaflops of performance out of it, but it's not a CPU based system, so no software will port to it. [1] https://github.com/mikewarot/Bitgrid