Bitgrid

, the latency for a given stream would be horrible, but you could have millions of parallel streams. To do this, you have to map the directed graph to hardware. In an FPGA this can take days because of the special modules, etc. This makes programming a nightmare. With a BitGrid, you can just use a greedy mapping algorithm, and Bob's your Uncle. Because every cell is essentially the worlds smallest Excel Sheet cell, it's easy to know all of the dependencies for any given cell. You can move cells, rotate them, flip and mirror them if you need to maximize the utilization of hardware, or want to wall off a given graph inside walls for isolation. Until recently, I've always thought of it as a chip, but recently I've come to see that you could just as well take a farm of RP2040 chips and have them all running slow simulators of a fairly huge BitGrid chips, and network them through their I/O pins to make an arbitrary size array, cheap! The BitGrid topology thus becomes a universal computing solvent. Scaling anything that can be expressed as the directed graph can be run very slowly on a CPU with a lot of RAM/Disk, or quickly on silicon, with identical results. I think this could scale to PetaFlops quite cheaply (a few runs through TinyTapeOut then scaling up) [1] https://github.com/mikewarot/Bitgrid [2] https://mikewarot.github.io/Bitgrid_C/bitgrid_sim.html [3] https://esolangs.org/wiki/Bitgrid

told with niceties.[4] [1] https://mikewarot.github.io/Bitgrid_C/bitgrid_sim.html [2] https://github.com/mikewarot/Bitgrid [3] https://tinytapeout.com/ [4] https://github.com/mikewarot/RateMyPhotos

r race conditions. If you give up and embrace latency, and the wasting of gates to route signal, you end up with a homogenous, isolinear core. (The same in any linear direction) You can rather easily shift a part in any direction, rotate it, and flip it. You can route around defective cells (assuming the shift register chain doesn't break, of course). Latency goes to hell, but because every single operation is pipelined, your throughput can go through the roof, none of the data lines ever has to make it all the way across the chip, except the clock signals. The shift registers, and only have to load things before the computing starts, so they don't have to be fast at all. [1] https://mnemocron.github.io/2023-12-08-DIY-FPGA-diary-1/ [2] https://esolangs.org/wiki/Bitgrid [3] https://github.com/mikewarot/Bitgrid [4] https://hackaday.com/2012/11/01/discrete-fpga-will-probably-... [5] https://web.archive.org/web/20150621104100/http://blog.notdo... [6] https://github.com/Arachnid/dfpga/tree/master