KVkvemkon·Jul 7, 2025
There is mature GHDL https://github.com/ghdl/ghdl and rather new NVC https://github.com/nickg/nvc.
In SUS Lang: The SUS Hardware Description Languagenickg
nvc
C2016–2025
nickg / nvc
nvc
VHDL compiler and simulator
4Distinct people
4Mentions
0Explicit recommenders
906GitHub stars
What to know before exploring
What it is
VHDL compiler and simulator
GitHub
Where it is used
No documented product use has been verified yet.
What people are saying
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Also in these discussions
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This week on Hacker News
Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 3:56:07 PM UTC.
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Mentions over time
HN mentions by year4 dated mentions
Observed mentions: 2016-07-27 04:13:33 UTC to 2025-07-07 20:21:09 UTC.
Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.
View mention counts and date ranges
| Period | Start (UTC) | End (exclusive, UTC) | Mentions | Submissions | Comments |
|---|---|---|---|---|---|
| 2016 | 2016-01-01 00:00:00 UTC | 2017-01-01 00:00:00 UTC | 1 | 0 | 1 |
| 2017 | 2017-01-01 00:00:00 UTC | 2018-01-01 00:00:00 UTC | 0 | 0 | 0 |
| 2018 | 2018-01-01 00:00:00 UTC | 2019-01-01 00:00:00 UTC | 0 | 0 | 0 |
| 2019 | 2019-01-01 00:00:00 UTC | 2020-01-01 00:00:00 UTC | 0 | 0 | 0 |
| 2020 | 2020-01-01 00:00:00 UTC | 2021-01-01 00:00:00 UTC | 0 | 0 | 0 |
| 2021 | 2021-01-01 00:00:00 UTC | 2022-01-01 00:00:00 UTC | 0 | 0 | 0 |
| 2022 | 2022-01-01 00:00:00 UTC | 2023-01-01 00:00:00 UTC | 1 | 0 | 1 |
| 2023 | 2023-01-01 00:00:00 UTC | 2024-01-01 00:00:00 UTC | 0 | 0 | 0 |
| 2024 | 2024-01-01 00:00:00 UTC | 2025-01-01 00:00:00 UTC | 0 | 0 | 0 |
| 2025 | 2025-01-01 00:00:00 UTC | 2026-01-01 00:00:00 UTC | 2 | 1 | 1 |
What Hacker News says
4 sourcesNVC: VHDL Compiler and Simulator
8 points · Open discussionYou can use a simulation program. One of the professional ones that I like is ModelSim.
You design your chip in VHDL or Verilog, compile it, and then make a (virtual) testbench in ModelSim. Then you run your design in ModelSim.
You can have a look at signals while it's running the simulation in simulated oscilloscopes or you can script a better view in Tcl/Tk or you can have the testbench assert stuff. The latter lets you do something like unit tests. I do that a lot.
Note that simulations are lies. So it's helpful to find obvious bugs--but in the real world all the signals run IN PARALLEL, and they can grow phase differences depending on the routing (which is generated). The simulation cannot test all the combinations (but of course the compiler tries to make the gate to gate timing work on its own).
Open source variants exist. I like ht
Read the rest
tps://github.com/nickg/nvc.git . In includes a compiler (from VHDL) and simulator. You can have nvc generate waveform outputs and look at those in gtkwave. It's neat. But it's not as full-featured as ModelSim.
Eventually, you can buy an FPGA development board like the Terasic DE10-Nano and download the program Quartus Prime and actually synthesize your design and load it on the board. You need a REALLY beefy computer to do the synthesis in finite time.
nvc (LLVM based) is also impressively complete for the number of people who have worked on it.
https://github.com/nickg/nvc
In Verifying ARM processors against the official ARM specification