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nukeykt
Nuked-MD-FPGA
Verilog2023–2023
nukeykt / Nuked-MD-FPGA

Nuked-MD-FPGA

Mega Drive/Genesis core written in Verilog

3Distinct people
3Mentions
0Explicit recommenders
316GitHub stars
REPOSITORY AT A GLANCE

What to know before exploring

What it is

Mega Drive/Genesis core written in Verilog

GitHub

Where it is used

No documented product use has been verified yet.

What people are saying

No recommendation phrase was found in the indexed comments.

No classified warning is attached to this page. Read the discussions before treating silence as approval.

Also in these discussions

No other repository is repeatedly linked in the same discussions.

This week on Hacker News

Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 5:04:57 PM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by week3 dated mentions

Observed mentions: 2023-08-03 21:38:56 UTC to 2023-11-28 02:56:39 UTC. Weeks start Monday, UTC.

0122023-07-31 00:00:00 UTC to 2023-08-07 00:00:00 UTC (exclusive): 2 mentions; 1 submissions, 1 commentsJul 312023-08-07 00:00:00 UTC to 2023-08-14 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2023-08-14 00:00:00 UTC to 2023-08-21 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2023-08-21 00:00:00 UTC to 2023-08-28 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2023-08-28 00:00:00 UTC to 2023-09-04 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2023-09-04 00:00:00 UTC to 2023-09-11 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2023-09-11 00:00:00 UTC to 2023-09-18 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2023-09-18 00:00:00 UTC to 2023-09-25 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2023-09-25 00:00:00 UTC to 2023-10-02 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 commentsSep 252023-10-02 00:00:00 UTC to 2023-10-09 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2023-10-09 00:00:00 UTC to 2023-10-16 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2023-10-16 00:00:00 UTC to 2023-10-23 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2023-10-23 00:00:00 UTC to 2023-10-30 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2023-10-30 00:00:00 UTC to 2023-11-06 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2023-11-06 00:00:00 UTC to 2023-11-13 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2023-11-13 00:00:00 UTC to 2023-11-20 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2023-11-20 00:00:00 UTC to 2023-11-27 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2023-11-27 00:00:00 UTC to 2023-12-04 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 commentsNov 27

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

View mention counts and date ranges
UTC ranges include their start and exclude their end. Select a period to filter the source evidence.
PeriodStart (UTC)End (exclusive, UTC)MentionsSubmissionsComments
Jul 312023-07-31 00:00:00 UTC2023-08-07 00:00:00 UTC211
Aug 72023-08-07 00:00:00 UTC2023-08-14 00:00:00 UTC000
Aug 142023-08-14 00:00:00 UTC2023-08-21 00:00:00 UTC000
Aug 212023-08-21 00:00:00 UTC2023-08-28 00:00:00 UTC000
Aug 282023-08-28 00:00:00 UTC2023-09-04 00:00:00 UTC000
Sep 42023-09-04 00:00:00 UTC2023-09-11 00:00:00 UTC000
Sep 112023-09-11 00:00:00 UTC2023-09-18 00:00:00 UTC000
Sep 182023-09-18 00:00:00 UTC2023-09-25 00:00:00 UTC000
Sep 252023-09-25 00:00:00 UTC2023-10-02 00:00:00 UTC000
Oct 22023-10-02 00:00:00 UTC2023-10-09 00:00:00 UTC000
Oct 92023-10-09 00:00:00 UTC2023-10-16 00:00:00 UTC000
Oct 162023-10-16 00:00:00 UTC2023-10-23 00:00:00 UTC000
Oct 232023-10-23 00:00:00 UTC2023-10-30 00:00:00 UTC000
Oct 302023-10-30 00:00:00 UTC2023-11-06 00:00:00 UTC000
Nov 62023-11-06 00:00:00 UTC2023-11-13 00:00:00 UTC000
Nov 132023-11-13 00:00:00 UTC2023-11-20 00:00:00 UTC000
Nov 202023-11-20 00:00:00 UTC2023-11-27 00:00:00 UTC000
Nov 272023-11-27 00:00:00 UTC2023-12-04 00:00:00 UTC101

What Hacker News says

3 sources
The reality is that the vast majority of these FPGA-based clones don't actually perfectly emulate the logic. They're using the same reverse engineering techniques the traditional emulator developers used and sometimes even the same community documentation. The results are often quite good, but they're making a new implementation that matches the observed behavior of the original system to the best of their abilities. Now there are some exceptions. Nuked MD FPGA[0] is a recent example of an FPGA recreation that is a fairly direct translation of the original logic using silicon die analysis. In this case, the logic is basically identical, but as you guessed the physical layout is different. Generally speaking, you write FPGA "gateware" in a language like Verilog or VHDL. These don't intrinsically have any information about the physical layo
Read the rest
ut of the logic which is handled by the toolchain instead. As wmf says, this is generally not a problem most of the time. For synchronous logic, either the total propagation delay is small enough for a single cycle or it isn't. The toolchain will estimate this delay and report whether you met timing or not for the configured clockspeed. Not everything you can do in silicon translates well to FPGAs (both clock edges is also generally not well supported for instance), but for the most part these things are easy enough to work around. [0] https://github.com/nukeykt/Nuked-MD-FPGA
In FPGAs and the renaissance of retro hardware
Kinda, sorta? This is like saying "a computer is not enough, you need a binary." What's here is the source code in Verilog. Once this is compiled by a Verilog toolchain, this produces a netlist (set of gates) which is synthesized into an actual bitstream (proprietary gate configuration file) for a specific FPGA hosted on a specific board. In this case, the project isn't very documented but it looks like fairly generic Verilog without a lot of vendor specific extensions. So, what you need is a Verilog toolchain which can synthesize the source code into a netlist, and then into a bitstream, and the right set of extra code to target an actual physical piece of hardware. Right now, it looks like the only board support that's checked into the repository is for the Icarus Verilog simulation environment: https://github.com/nukeykt/Nuked-MD-FPGA/
Read the rest
tree/main/icarus . But, the overall setup looks pretty simple and generic, so it should (hopefully) be possible to synthesize to your board of choice by reimplementing run.v and memstubs.v towards an actual hardware configuration. Basically what you'd want to do to start trying to run this on real hardware is to build a hosting environment which wired the inputs and outputs from `md_board.v` into the real hardware provided in your environment, possibly by integrating other soft-IP (ie - you could attach a cartridge emulator of some sort to the cartridge lines, your choice of video encoder to the video output, and so on).
In Nuked-MD-FPGA – Emulating Sega Mega Drive chipset using decapped chips photos

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