MMmmastrac·Mar 31, 2025
Any ideas if the mask ROM is scrambled? Apparently the P6 doesn't have a direct mask ROM : microcode relationship.
https://github.com/peterbjornx/p6tools
In Notes on the Pentium's microcode circuitrypeterbjornx
p6tools
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peterbjornx / p6tools
p6tools
Pentium II microcode (dis)assembler and (de)scrambler
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2Mentions
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24GitHub stars
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Pentium II microcode (dis)assembler and (de)scrambler
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Observed mentions: 2021-03-20 13:07:00 UTC to 2025-03-31 21:19:25 UTC.
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| Period | Start (UTC) | End (exclusive, UTC) | Mentions | Submissions | Comments |
|---|---|---|---|---|---|
| 2021 | 2021-01-01 00:00:00 UTC | 2022-01-01 00:00:00 UTC | 1 | 0 | 1 |
| 2022 | 2022-01-01 00:00:00 UTC | 2023-01-01 00:00:00 UTC | 0 | 0 | 0 |
| 2023 | 2023-01-01 00:00:00 UTC | 2024-01-01 00:00:00 UTC | 0 | 0 | 0 |
| 2024 | 2024-01-01 00:00:00 UTC | 2025-01-01 00:00:00 UTC | 0 | 0 | 0 |
| 2025 | 2025-01-01 00:00:00 UTC | 2026-01-01 00:00:00 UTC | 1 | 0 | 1 |
What Hacker News says
2 sourcesOh for sure. Even if it’s the P6’s microcode (the first with updatable code), I’d take it. I’ve always wondered what microcode looks like in these processors, and how it functions. There is “p6tools”[0][1] which looks interesting. But if Intel released info on it, that’d be really cool.
Sidenote: Ken Shirriff has reverse engineered the ARM1’s microcode,[2] but it’s a “horizontal” microcode (bits control CPU blocks directly) while x86 uses “vertical” (RISC-like) microcode.
[0]: https://github.com/peterbjornx/p6tools
[1]: https://www.youtube.com/watch?v=4oFOpDflJMA (slides: https://hardwear.io/netherlands-2020/presentation/under-the-...)
[2]: http://www.righto.com/2016/02/reverse-engineering-arm1-proce...
In Undocumented x86 instructions in Intel CPUs that can modify microcode