z80-open-silicon

There are a number of efforts to make low volume production of compatible parts - see https://github.com/rejunity/z80-open-silicon There are also FPGA emulated versions.

There is a drop in compatible FOSS clone of Z80 https://github.com/rejunity/z80-open-silicon

FYI this how chip looks right now in the 5 mm^2 configuration. https://github.com/rejunity/z80-open-silicon/blob/main/docs/... The colourful lines in the middle are the metal wires (layers 2,3 & 4) displaying the interconnect inside the chip and connections to the I/O pads which in turn will be wirebonded to the external pins.

I like it! What about also "XORing" 80 somewhere on the bottom part of Z letter? Would you mind submitting a ticket "issue" with it please?: https://github.com/rejunity/z80-open-silicon/issues PS: both PNG and SVG would be handy.

Some folks are working on making a drop-in replacement for the Z80, as open source and free silicon. Git repo is here. https://github.com/rejunity/z80-open-silicon

But look here, it's even doing a switch-case over the opcode, which is very typical for a software CPU emulator: https://github.com/rejunity/z80-open-silicon/blob/974c7711b2... Instruction decoding on a real Z80 CPU doesn't work at all like that :) A non-emulator-approach would probably use the reverse engineered Z80 netlist from visual6502.org to base the design on, no idea if this is even doable with modern chip design tooling(?) If anything, the netlist is useful to verify the Verilog implementation (as is mentioned here in the readme: https://github.com/rejunity/z80-open-silicon?tab=readme-ov-f...)

That's the expected clock rate for the TT07 run... but Tiny Tapeout designs only have 8 in, 8 out, and 8 bidirectional IOs (plus a reset and clock input) available, so they're using a multiplexing strategy where the Z80 clock runs at 1/4 of the base clock rate and alternates between control signals, A0-A7, control signals, and A8-A15 on the OUT pins: https://github.com/rejunity/z80-open-silicon/blob/68438f0019... So you'd get an effective 12.5MHz Z80 clock and need a bit of external logic to demultiplex the full IO interface. Still not too shabby! The goal (per the project README) appears to be to prototype with TT07 and then look into taping out standalone with ChipIgnite in QFN44 and DIP40 packages (which would be able to have the full traditional Z80 bus interface and run at the full clock rate).

Because it's a Verilog implementation which is much closer to a software CPU emulator than the real thing (e.g. it has nothing to do with the original Z80 "transistor layout"). For instance here's the LD A,(DE) "instruction payload": https://github.com/rejunity/z80-open-silicon/blob/974c7711b2... And here's the same machine cycle in my software emulator: https://github.com/floooh/chips/blob/bd1ecff58337574bb46eba5... Both set the address bus to the content of the DE register (and at the same time the MREQ|RD pins need to be set somewhere to indicate a memory read to the outside world, in my emulator this happens in the _mread macro), and in the next clock cycle load the data bus into the A register. What's interesting though is that the Verilog implementation doesn't seem to update the internal WZ register with DE+1, which makes me wonder

This page says 50 MHz. https://github.com/rejunity/z80-open-silicon/blob/main/docs/...