riscv-elf-psabi-doc

Thanks for the context, but what I am criticising is this part: > it became allowed to use @bitCast to reinterpret a [3]u8 as a u24 This cant't make sense unless u24 is defined to be 24bits in the first place. It is just silly to allow something like this. It would make so much more sense to me if they started disallowing this or just even print a deprecation notice for it for one release version. > Useful for larger integers than int16_t while saving 25% over a 32-bit value You can't even do []u24 in zig as far as I can remember and understand anyway so this is only happening in a packed struct context. C doesn't mandate padding but C compilers allow having pointers and arrays of irregular _BitInt types as far as I can understand. In this [1] document, in Abi considerations section, it writes that it is defined to have next-power-of-two

I agree; wasm would be a better choice, as it's specifically designed for this use case. RISC-V is designed for hardware implementation, not to be an IR, which means that things are more verbose than they need to be. For example, accessing an arbitrary 64-bit address requires 6 instructions [1] in RISC-V, whereas in Wasm you can just do it. Even more important than ISA differences, though, is that with Wasm you get WASI, which saves you a whole lot of time creating a sandboxed system interface. [1]: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/38...

I hope Microsoft does not plan on violating LP64D[0] on its RISC-V port. 0. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/ma...

Sure. It's the section here https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/ma... It's that structs of two simple fields need to be passed in registers. And more specifically that this rule is relevant for mixed integer and floating point fields. It's a very specific rule that requires a ton of code to implement compared to the integer calling convention. And again like the weird AMD64 convention likely invented to squeeze out a theoretical few cycles that never occur outside microbenchmarks