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riscv-software-src
riscv-pk
C2018–2020
riscv-software-src / riscv-pk

riscv-pk

RISC-V Proxy Kernel

3Distinct people
4Mentions
0Explicit recommenders
712GitHub stars
REPOSITORY AT A GLANCE

What to know before exploring

What it is

RISC-V Proxy Kernel

GitHub

Where it is used

No documented product use has been verified yet.

What people are saying

No recommendation phrase was found in the indexed comments.

No classified warning is attached to this page. Read the discussions before treating silence as approval.

Also in these discussions

No other repository is repeatedly linked in the same discussions.

This week on Hacker News

Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 3:56:07 PM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by month4 dated mentions

Observed mentions: 2018-07-01 14:26:15 UTC to 2020-01-15 17:07:55 UTC.

0122018-07-01 00:00:00 UTC to 2018-08-01 00:00:00 UTC (exclusive): 2 mentions; 0 submissions, 2 commentsJul 20182018-08-01 00:00:00 UTC to 2018-09-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2018-09-01 00:00:00 UTC to 2018-10-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2018-10-01 00:00:00 UTC to 2018-11-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2018-11-01 00:00:00 UTC to 2018-12-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2018-12-01 00:00:00 UTC to 2019-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2019-01-01 00:00:00 UTC to 2019-02-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2019-02-01 00:00:00 UTC to 2019-03-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2019-03-01 00:00:00 UTC to 2019-04-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2019-04-01 00:00:00 UTC to 2019-05-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 commentsApr 20192019-05-01 00:00:00 UTC to 2019-06-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2019-06-01 00:00:00 UTC to 2019-07-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2019-07-01 00:00:00 UTC to 2019-08-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2019-08-01 00:00:00 UTC to 2019-09-01 00:00:00 UTC (exclusive): 1 mentions; 1 submissions, 0 comments2019-09-01 00:00:00 UTC to 2019-10-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2019-10-01 00:00:00 UTC to 2019-11-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2019-11-01 00:00:00 UTC to 2019-12-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2019-12-01 00:00:00 UTC to 2020-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2020-01-01 00:00:00 UTC to 2020-02-01 00:00:00 UTC (exclusive): 1 mentions; 1 submissions, 0 commentsJan 2020

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

View mention counts and date ranges
UTC ranges include their start and exclude their end. Select a period to filter the source evidence.
PeriodStart (UTC)End (exclusive, UTC)MentionsSubmissionsComments
Jul 20182018-07-01 00:00:00 UTC2018-08-01 00:00:00 UTC202
Aug 20182018-08-01 00:00:00 UTC2018-09-01 00:00:00 UTC000
Sep 20182018-09-01 00:00:00 UTC2018-10-01 00:00:00 UTC000
Oct 20182018-10-01 00:00:00 UTC2018-11-01 00:00:00 UTC000
Nov 20182018-11-01 00:00:00 UTC2018-12-01 00:00:00 UTC000
Dec 20182018-12-01 00:00:00 UTC2019-01-01 00:00:00 UTC000
Jan 20192019-01-01 00:00:00 UTC2019-02-01 00:00:00 UTC000
Feb 20192019-02-01 00:00:00 UTC2019-03-01 00:00:00 UTC000
Mar 20192019-03-01 00:00:00 UTC2019-04-01 00:00:00 UTC000
Apr 20192019-04-01 00:00:00 UTC2019-05-01 00:00:00 UTC000
May 20192019-05-01 00:00:00 UTC2019-06-01 00:00:00 UTC000
Jun 20192019-06-01 00:00:00 UTC2019-07-01 00:00:00 UTC000
Jul 20192019-07-01 00:00:00 UTC2019-08-01 00:00:00 UTC000
Aug 20192019-08-01 00:00:00 UTC2019-09-01 00:00:00 UTC110
Sep 20192019-09-01 00:00:00 UTC2019-10-01 00:00:00 UTC000
Oct 20192019-10-01 00:00:00 UTC2019-11-01 00:00:00 UTC000
Nov 20192019-11-01 00:00:00 UTC2019-12-01 00:00:00 UTC000
Dec 20192019-12-01 00:00:00 UTC2020-01-01 00:00:00 UTC000
Jan 20202020-01-01 00:00:00 UTC2020-02-01 00:00:00 UTC110

What Hacker News says

4 sources
Please don't spread misinformation. RISC-V has a well-thought out machine layer which is open source in all existing implementations[1]. You can easily modify the M layer if it's interfering with the performance or security of your OS. The virtualization extension hasn't been finalized (but they are working with key KVM people), but it will perform a lot better than a theoretically pure self-virtualizable ISA. [1] https://github.com/riscv/riscv-pk
In A survey of attacks against Intel x86 over last 10 years (2015) [pdf]
On your second question about real-time support, I think the answer is (probably) yes although it depends a bit on precisely what you mean by "real time". I'm assuming you mean as a hard real time microcontroller. First off there is an Intel SMM-like layer (M mode) running under the operating system. Unlike Intel it's all open source. So if you find that something in M mode is taking too long and disturbing your real time guarantees, you at least have a hope of fixing it. Obviously Linux is no use for hard real time, but in the HiFive Unleashed board there is a separate RV32 core on the side which actually does nothing except spinning in M mode. It literally runs this loop: https://github.com/riscv/riscv-pk/blob/600ff370c65ba99d2103a... You could have this spare core do anything you want while running Linux on the application cores.
Read the rest
I believe it has full access to RAM and GPIO pins. Secondly there is a 96Boards compatible expansion header with some but not very many GPIO pins, see section 8.2 here: https://static.dev.sifive.com/HiFive-Unleashed-Getting-Start... Thirdly the clock currently runs at a constant speed (but settable), so there's no power management, both a good and a bad thing, but probably good for real-time.
In SiFive to release source code to initialize HiFive Unleashed RISC-V board

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