riscv

riscv-bitmanip

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riscv / riscv-bitmanip

riscv-bitmanip

Working draft of the proposed RISC-V Bitmanipulation extension

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REPOSITORY AT A GLANCE

What to know before exploring

What it is

Working draft of the proposed RISC-V Bitmanipulation extension

GitHub

Where it is used

No documented product use has been verified yet.

What people are saying

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Also in these discussions

riscv/riscv-crypto · linked in 2 of the same discussions
riscvarchive/riscv-v-spec · linked in 2 of the same discussions

Mentioned in the same Hacker News threads. That is not proof they are substitutes.

This week on Hacker News

Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 5:04:57 PM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by year17 dated mentions

Observed mentions: 2019-06-08 07:41:29 UTC to 2025-02-09 21:04:20 UTC.

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

View mention counts and date ranges

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Period	Start (UTC)	End (exclusive, UTC)	Mentions	Submissions	Comments
2019	2019-01-01 00:00:00 UTC	2020-01-01 00:00:00 UTC	5	1	4
2020	2020-01-01 00:00:00 UTC	2021-01-01 00:00:00 UTC	5	0	5
2021	2021-01-01 00:00:00 UTC	2022-01-01 00:00:00 UTC	3	0	3
2022	2022-01-01 00:00:00 UTC	2023-01-01 00:00:00 UTC	1	0	1
2023	2023-01-01 00:00:00 UTC	2024-01-01 00:00:00 UTC	2	0	2
2024	2024-01-01 00:00:00 UTC	2025-01-01 00:00:00 UTC	0	0	0
2025	2025-01-01 00:00:00 UTC	2026-01-01 00:00:00 UTC	1	0	1

What Hacker News says

17 sources

ryao·Feb 9, 2025

It just occurred to me that Clang and GCC did not necessarily fail to use conditional moves in your examples. While they failed to use explicit cmov instructions, cmp/jmp 1 instruction/mov is actually an idiom for an implicit cmov. Some CPU instruction decoders are able to turn it into a cmov without an explicit cmov instruction. In the case of RISC-V, the designers are philosophically opposed to explicit cmov instructions and expect compilers to generate this idiom for CPUs that support cmov. I asked them to implement cmov virtual instructions to be nice to people reading RISC-V assembly, but I am not sure if anything will come of it: https://github.com/riscv/riscv-bitmanip/issues/185 I do not know if any x86 CPUs recognize the implicit cmov idiom offhand, but if any do, then while an extra instruction was used, the conditional move woul

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d still be done on those that recognize the idiom. By the way, I just noticed a case where you really don’t want the compiler to generate a cmov, explicit or otherwise since it would risk division by zero: https://github.com/openzfs/zfs/commit/f47f6a055d0c282593fe70... Here is a godbolt link showing some output: https://www.godbolt.org/z/4daKTKqfr Interestingly, Clang correctly does not generate a cmov (implicit or explicit) for the outer ternary operation, while it does generate an explicit cmov for the inner ternary operator in MIN() without -mllvm -x86-cmov-converter=false. Passing -mllvm -x86-cmov-converter=false to Clang does not change the output, which makes Clang’s behavior correct. GCC will not generate cmov for either ternary operator, which while also technically correct, is slow. This could still have been an implicit conditional move had GCC not avoided the implicit cmov idiom. Using GCC’s __builtin_expect_with_probability() in MIN() does not cause GCC to change its output. If we remove the outer ternary, GCC will happily generate a cmov instruction. Given that GCC generally assumes that undefined behavior is not invoked to make code faster and will happily generate the cmov when there is a division by 0 bug, it is odd that upon seeing a check that verifies the assumption GCC made is true, GCC decides to stop generating a cmov. I am sure the way GCC does things is much more complicated than my interpretation of the output, but the behavior is odd enough to merit a comment.

In Don't "optimize" conditional moves in shaders with mix()+step()

camel-cdr·Aug 13, 2023

The bit manipulation [0] extension has been ratified for a while now and is part of the RVA22 application extension profile [1]. You can already buy SOCs that support it, e.g. vision five 2 and star64. Interestingly the risc-v vector extension [2] has it's own popcount instructions for vector registers/register masks. This is needed, because the scalable architecture doesn't guarantee that a vector mask can fit into a 64 bit register, so vector masks are stored in a single LMUL=1 register. This works really well, because with LMUL=8 and SEW=8 you get 100% utilization of the single LMUL=1 vector register. Another interesting thing is that the vector crypto extension will likely introduce a element wise popcount instruction [3]. [0] https://github.com/riscv/riscv-bitmanip [1] https://github.com/riscv/riscv-profiles [2] https://github.com/ri

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scv/riscv-v-spec [3] https://github.com/riscv/riscv-crypto/blob/master/doc/vector...

In Popcount CPU instruction (2019)

mncharity·Jan 14, 2023

Here's the ratified spec[1]. And some class slides[2]. And a list of other recent extensions[3]. [1] https://github.com/riscv/riscv-bitmanip/releases/download/1.... from https://github.com/riscv/riscv-bitmanip/releases . [2] https://courses.cs.washington.edu/courses/cse481a/20sp/notes... [3] https://wiki.riscv.org/display/HOME/Recently+Ratified+Extens...

In TinyEMU – x86 and RISC-V emulator, small and simple while being complete

cbm-vic-20·Dec 13, 2022

These are the cpop and cpopw instructions. https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/i...

In A neat XOR trick

Pet_Ant·Dec 2, 2021

Yoe maybe interested in the just ratified "RISC-V Bit-Manipulation ISA-extensions" https://github.com/riscv/riscv-bitmanip/releases/download/1....

In RISC-V Int. Ratifies 15 New Specs, Opening Up New RISC-V Design Possibilities

bem94·Dec 2, 2021

Direct links to some of the latest specs: - Scalar crypto: https://github.com/riscv/riscv-crypto/releases - Vectors: https://github.com/riscv/riscv-v-spec/releases - Bitmanip: https://github.com/riscv/riscv-bitmanip/releases

In RISC-V Int. Ratifies 15 New Specs, Opening Up New RISC-V Design Possibilities

rwmj·Sep 10, 2021

https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/_...

In HiFive Unmatched – A RISC-V Linux development platform

throwaway_pdp09·Sep 27, 2020

I guess these are the bitmanip stuff you mention https://github.com/riscv/riscv-bitmanip They're a proposal only (and I don't think they're an official proposal), and having read them it seems the guy just shoehorned in anything he could think of. I'm curious to see how much of it will be accepted.

In RISC-V: What’s Missing and Who’s Competing

CalChris·Sep 26, 2020

I like RISC-V and I like RV32E, the 16-register variant which is still 'OPEN' and not yet ratified. I think RVC is a very elegant compressed instruction approach; it can address 8 registers and is part of RV32E. RVC is far better than the Thumb or MIPS16 modes. Yeah, I like RISC-V generally, especially the base and the vector extension. However, they really went off the rails with the Bit Manipulation Extensions [1] still in draft form. Compare bfp which mixes control + data in the same register with ARMv8 bfi. It's only been added since the 0.92 draft but it seems to me very un-RISC-like. [1] https://github.com/riscv/riscv-bitmanip

In RISC-V: What’s Missing and Who’s Competing

avianes·Jul 24, 2020

> a = (x & c) | (y & ~c) > is a branch-free conditional assignment, and only works with c = 0 or ~0. Using this hack only makes sense if there is no "conditional move". But the bitmanip risc-v extension offers a "conditional move" (cmov) [1]. With the addition of this operation there's no longer a need to use "0/-1" instead of "0/1". [1]: https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip... page 36 PS: You may notice that there's also an operation (cmix: conditional max) to do what you're suggesting: rd = (rs1 & rs2) | (rs3 & ~rs2) Which allows to mix the bits of two registers.

In Will RISC-V Revolutionize Computing?

Symmetry·Jul 8, 2020

The B extension is going to add that. https://github.com/riscv/riscv-bitmanip Also conditional move which you really need for a lot of reasons but especially to avoid timing attacks in cryptography.

In Ariane RISC-V CPU – An open source CPU capable of booting Linux

tveita·Mar 2, 2020

On the other hand the instruction set extensions can be bulky. For instance the bit manipulation set at https://github.com/riscv/riscv-bitmanip adds frequently used operations like conditional move and population count, but also adds things like "multiply binary matrix" and "generalized or-combine", which I'm not sure even exists in X86 or AMD64.

In Open Source Hardware: The Rise of RISC-V

blacksmythe·Aug 23, 2019Submission

Verilog for all proposed RISC-V bitmanip instructions

3 points · Open discussion

legulere·Jun 22, 2019

At least for binary matrix multiplication there is precedent: https://github.com/riscv/riscv-bitmanip/wiki/bitmat

In Avoiding Instruction Cache Misses

ncmncm·Jun 19, 2019

I am waiting until the Bitmanip extension lands to get excited about RISC-V: https://github.com/riscv/riscv-bitmanip Just can't live without that popcount.

In Debian Riscv64 port in mid 2019

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