riscv-p-spec

I thought I had read somewhere that the Packed SIMD (P) extension was still going to be developed for implementations that don't need the full-blown Vector (V) extension, for example, embedded processors for digital signal processing. https://github.com/riscv/riscv-p-spec/ https://github.com/riscv/riscv-v-spec/

"It does not natively have common instructions like add multiply"; this is is misinformation. Almost anybody implementing RISC-V -- esp if they are targeting an MPU instead of MCU -- is implementing instruction variants which include signed and unsigned multiply and divide, and my understanding is the P and probably V extensions include various add-multiply instructions. https://github.com/riscv/riscv-p-spec/blob/master/P-ext-prop... See section 3.2. The instruction set is specified in a 'modular' fashion and has standards for various extensions, including compact instructions, vector extensions, etc. Compilers like GCC and LLVM support targeting these extensions. I'm not saying AMD should make a RISC-V CPU, but if they were to hypothetically do that, they'd clearly be including a pile of the ratified extensions.