riscv-code-size-reduction

There's far more than 2. Even just taking RV32I, you have M, A, F, D standard extensions which are all optional. A CPU could include any combination of these, so you have 3! possible instruction sets off the start line. But let's assume we're working with G (which means all of IMAFD) Many PC grade processors will support some or all of extensions B (bitmanip), T (transactional memory), P (packed SIMD), V (Vectors), C (compressed instructions), RV64I, RV128I, Q (quad floats), and not to mention all the non-standard extensions. See: https://groups.google.com/a/groups.riscv.org/g/isa-dev/searc... for non-standard extensions. You also have vendor specific extensions such as those from Huawei: https://github.com/riscv/riscv-code-size-reduction/tree/main... As an application developer, finding the right set of features for your users will mean

In 64bit, RISC-V does easily beat ARM and everything else. In 32bit, it is about as good as m68k and x86, which are quite dense. A good result. Just not as small as ARM thumb/thumb2. However, RISC-V is not done yet; it will see further improvements, coming from B extension (already ratified, significant for size, and yet wasn't in the test) and from the ongoing Zc size-reduction work[0], which does already achieve a sizable reduction[1]. 0. https://github.com/riscv/riscv-code-size-reduction 1. https://docs.google.com/spreadsheets/d/1bFMyGkuuulBXuIaMsjBI...

https://github.com/riscv/riscv-code-size-reduction is the place to check.