oberon-riscv

Readers encountering this project for the first time should be aware that the earlier Oberon-on-RISC-V project <https://github.com/solbjorg/oberon-riscv> (HN discussion: <https://news.ycombinator.com/item?id=25497002>) exists and was already discussed on the mailing list: <https://lists.inf.ethz.ch/pipermail/oberon/2026/017161.html>

This project is still a great example of a complete computer design, starting from Niklaus Wirth's own RISC5 CPU (not a RISC-V) and very simple peripherals over the OS, runtime/garbage collector, compiler, GUI and simple example applications. One problem of the original implementation is that it was based on an old Xilinx Spartan 3 development board. This is not only no longer available, but it is one of the few FPGA boards that used 32 bit wide fast (12 ns IIRC) asynchronous SRAM chips. Wirth's hardware design relies heavily on this. Some years ago, there was a compatible board, the OberonStation. However, it seems this is no longer manufactured: https://pcper.com/2015/12/meet-the-oberonstation-kid-friendl... However, some modified designs exist that implement a cache in FPGA block RAM and an SDRAM controller. These can be used with more

Thanks for the link! Adapting the Project Oberon compiler code generation isn't that difficult, but the devil is in the details :). My student Rikke described some of the challenges porting Project Oberon to RISC-V in her project report (https://github.com/solbjorg/oberon-riscv/blob/master/report....). I assume that the most time-consuming task to get Project Oberon to run on ARM/Raspberry Pi would be to write device drivers for more complex devices, e.g. USB and Ethernet. These could be written in Oberon (which would be a considerable effort) or possibly be abstracted by using a bare-metal hypervisor that supports VirtIO device abstractions, e.g. Vmware ESXI. This way, one would only have to implement VirtIO drivers in Oberon, which is considerably less complex. Connecting a PS/2 keyboard and mouse instead of USB might also be an alterna

The original Wirth RISC5 version runs in 1 MB RAM on an ancient Xilinx FPGA board. The RISC-V binaries are a bit larger, but still runs in 1 MB (but more is possible). A bit too large for typical block RAM sizes of affordable FPGAs, unfortunately. Some details on the port and the binary size differences can be found in the project report: https://github.com/solbjorg/oberon-riscv/blob/master/report....