CBcbHXBY1D·Sep 26, 2017
Yep and there's https://github.com/SpinalHDL/VexRiscv
But admittedly, SpinalHDL is basically Chisel.
In BOOM v2: an open-source out-of-order RISC-V coreSpinalHDL
VexRiscv
Assembly2017–2026
SpinalHDL / VexRiscv
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
13Distinct people
17Mentions
0Explicit recommenders
3.3KGitHub stars
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What it is
A FPGA friendly 32 bit RISC-V CPU implementation
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Where it is used
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This week on Hacker News
Nov 8–Nov 15 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/15/2026, 5:05:26 PM UTC.
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Mentions over time
HN mentions by year17 dated mentions
Observed mentions: 2017-07-19 10:19:55 UTC to 2026-05-23 17:37:10 UTC.
* An incomplete calendar period is marked with an outlined bar. Its count is not directly comparable with a full period.
Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.
View mention counts and date ranges
| Period | Start (UTC) | End (exclusive, UTC) | Mentions | Submissions | Comments |
|---|---|---|---|---|---|
| 2017 | 2017-01-01 00:00:00 UTC | 2018-01-01 00:00:00 UTC | 5 | 1 | 4 |
| 2018 | 2018-01-01 00:00:00 UTC | 2019-01-01 00:00:00 UTC | 0 | 0 | 0 |
| 2019 | 2019-01-01 00:00:00 UTC | 2020-01-01 00:00:00 UTC | 1 | 0 | 1 |
| 2020 | 2020-01-01 00:00:00 UTC | 2021-01-01 00:00:00 UTC | 4 | 0 | 4 |
| 2021 | 2021-01-01 00:00:00 UTC | 2022-01-01 00:00:00 UTC | 2 | 0 | 2 |
| 2022 | 2022-01-01 00:00:00 UTC | 2023-01-01 00:00:00 UTC | 1 | 0 | 1 |
| 2023 | 2023-01-01 00:00:00 UTC | 2024-01-01 00:00:00 UTC | 0 | 0 | 0 |
| 2024 | 2024-01-01 00:00:00 UTC | 2025-01-01 00:00:00 UTC | 0 | 0 | 0 |
| 2025 | 2025-01-01 00:00:00 UTC | 2026-01-01 00:00:00 UTC | 2 | 1 | 1 |
| 2026 (partial) | 2026-01-01 00:00:00 UTC | 2027-01-01 00:00:00 UTC | 2 | 0 | 2 |
What Hacker News says
5 sourcesCached an uncached memory access are currently staticaly specified by range :
https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/s...
From 0xF000000 to 0xFFFFFFFF access will be uncached.
In An FPGA-friendly 32-bit RISC-V CPU implementation> USB has an actual PHY hardware spec for exactly that reason. And I'm not sure I buy your GPIO argument, not a hardware engineer but I've known several who all swear never to use fab-supplied GPIO blocks.
It's not "what does the the external spec require", it's "how do we achieve that at a given fab process". Ie. how do you achieve specific slew rate etc. on a given process?
> It may well be that DRAM's analog requirements are fab-specific (though I'd be a little surprised if it were that bad: these are full swing classic bus signals), but nonetheless most of the complexity in these controllers is in the logic side: clocking, refresh, bank mapping, ECC, etc... That's all stuff we could (and should) be writing in open source HDL.
There's plenty of open source implementations for the digital side of things. On this very github project:
h
In An FPGA-friendly 32-bit RISC-V CPU implementationYes, silicon implementation provide the JTAG, but it's very likely their implementation will not be reusable for FPGA project (including JTAG debug things) because of their over complicated (but powerfull) solutions which would consume way to much area and restrict the FMax.
Then this specific VexRiscv ecosystem also provide a basic SoC with an multi master AXI4 inteconnect, SDRAM controller, embedded ram, APB3 interconnect, some slave like GPIO, UART, Timer, VGA. It's not incredible, but it's already a starting point ^^
See https://github.com/SpinalHDL/VexRiscv#briey-soc
In An FPGA-friendly 32-bit RISC-V CPU implementationAn FPGA-friendly 32-bit RISC-V CPU implementation
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