iverilog

Iverilog is a Verilog simulator. [1] Yosys [2] can synthesize Verilog to a variety of things, including simplified Verilog, cell netlists for ASICs and FPGAs (requiring further conversion), and also directly to the bytestream, for some Lattice FPGAs. Both are fully open source tools. Not as sophisticated as the commercial tools, and the Verilog dialect that is common between the two, is quite minimal, almost painfully so. But it works! A couple years ago I tested yosys with some code a little simpler than yours - a Verilog PDP-8 processor. Yosys turned it into a network of about 100 flip-flops and 800 NAND gates that, in principle, could be wired up out of TTL chips or made into an IC. [1] https://github.com/steveicarus/iverilog [2] https://github.com/YosysHQ/yosys

Icarus is still around. Stephen Williams has been steadfastly working on it over the years. http://iverilog.icarus.com/ https://github.com/steveicarus/iverilog I use it almost daily. It is a really nice Verilog simulator. I also use Verilator, ModelSim and other sims too . All of them find different issues with the code. The linter in Verilator is very nice to use to get rapid feedback.