DAdaedalus-·Oct 29, 2025
Try neorv32: https://github.com/stnolting/neorv32
In Berkeley Out-of-Order RISC-V Processor (Boom) (2020)stnolting
neorv32
VHDL2021–2025
stnolting / neorv32
neorv32
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
8Distinct people
12Mentions
0Explicit recommenders
2.3KGitHub stars
What to know before exploring
What it is
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
GitHub
Where it is used
No documented product use has been verified yet.
What people are saying
No recommendation phrase was found in the indexed comments.
No classified warning is attached to this page. Read the discussions before treating silence as approval.
Also in these discussions
No other repository is repeatedly linked in the same discussions.
This week on Hacker News
Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 5:04:57 PM UTC.
No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.
Mentions over time
HN mentions by year12 dated mentions
Observed mentions: 2021-03-28 07:31:50 UTC to 2025-10-29 15:20:32 UTC.
Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.
View mention counts and date ranges
| Period | Start (UTC) | End (exclusive, UTC) | Mentions | Submissions | Comments |
|---|---|---|---|---|---|
| 2021 | 2021-01-01 00:00:00 UTC | 2022-01-01 00:00:00 UTC | 7 | 3 | 4 |
| 2022 | 2022-01-01 00:00:00 UTC | 2023-01-01 00:00:00 UTC | 3 | 3 | 0 |
| 2023 | 2023-01-01 00:00:00 UTC | 2024-01-01 00:00:00 UTC | 0 | 0 | 0 |
| 2024 | 2024-01-01 00:00:00 UTC | 2025-01-01 00:00:00 UTC | 0 | 0 | 0 |
| 2025 | 2025-01-01 00:00:00 UTC | 2026-01-01 00:00:00 UTC | 2 | 0 | 2 |
What Hacker News says
12 sourcesSince Rust is not directly hardware, here is a nice tutorial on some simple OS basics: https://operating-system-in-1000-lines.vercel.app/en/
There was also some Rust specific OS tutorial somewhere that was written nicely, but I can't find it right now.
Also if you want to get real hardware, there is the neorv32 that has nice documentation: https://stnolting.github.io/neorv32/ https://github.com/stnolting/neorv32
It's a risc-v core written in VHDL
In Easy RISC-VNEORV32: A tiny, embedded and free-of-charge open-source RISC-V SoC
40 points · Open discussionAdding newlib system calls to a bare-metal RISC-V platform
2 points · Open discussionAdding custom RISC-V instructions to an open-source rv32 SoC
54 points · Open discussionThis is a tiny (less than 200 LUTs) Physical Unclonable Function hardware module for FPGAs. It provides a unique 96-bit "fingerprint" that can be used for security-related applications like key-generation or authentication.
The fingerprint is defined by the FPGA's semiconductor characteristics. The same bitstream will lead to different fingerprints when programmed to different FPGAs of the same type.
The whole design is written in platform-independent VHDL. No device-specific macros, primitives or attributes are used at all so the design can be implemented on any FPGA (tested on Intel, Lattice and (in-progress) Xilinx).
(the "platform-agnostic" concept/technique was taken from the NEPORV32 TRNG -> https://github.com/stnolting/neorv32)
A few bits of the raw fingerprint from the module are quite noisy, so a software post-processing is requi
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red. I have implemented a simple "averaging" mechanism here. Error correction codes might be much better - but I am still fighting with the theory behind them ;)
I have tested the design on several FPGAs with promising results (see GitHub page). However, I still need to do more long-time testing to ensure stability of the fingerprint.
Feedback is highly appreciated!
As long as FPGAs are available to consumers, it will be possible to have a computer running on open hardware. On the front page right now is this project: https://github.com/stnolting/neorv32
It's possible right now to have an FPGA running an open-source RISC-V implementation. The software isn't there yet, but I expect this to change as more RISC-V boards get on the market. God knows how useful this 'bootleg' computer will be, but it's a foundation to build on, at least. There's already work on porting Debian to RISC-V.
https://archive.fosdem.org/2019/schedule/event/riscvdebian/a...
And with a free, open ISA, it's not impossible for smaller, independent manufacturers to crop up and produce their own chips, especially given that the US is now investing in chip-fab. (if there is demand. If nobody cares that they don't own their machines, we
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were screwed from the start.)
I see a lot more hardware content on Youtube nowadays. Channels like Ben Eater are educating people on how computers work, and more accessible FPGAs may help create a more flexible environment for hardware.
Why not link to the GitHub?`
https://github.com/stnolting/neorv32
Also the Documentation
https://stnolting.github.io/neorv32/
This is absolutely one of the best documented free hardware projects that I have ever seen. Most company documentation is worse by far.
In NEORV32: A customizable RISC-V SoCOpen-source soft-core RISC-V SoC with gdb support
94 points · Open discussionOpen-source RISC-V soft-core NEORV32 adds on-chip debugger support
2 points · Open discussionTFA: This project is still active but is currently shelved as I am focusing on the NEO430's "big brother": The RISC-V-powered 32-bit NEORV32 https://github.com/stnolting/neorv32.
In The NEO430 ProcessorThe NEORV32 RISC-V soft-core microcontroller
1 points · Open discussion