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sylefeb
Silice
C++2020–2026
sylefeb / Silice

Silice

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

9Distinct people
12Mentions
0Explicit recommenders
1.4KGitHub stars
REPOSITORY AT A GLANCE

What to know before exploring

What it is

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

GitHub

Where it is used

No documented product use has been verified yet.

What people are saying

No recommendation phrase was found in the indexed comments.

No classified warning is attached to this page. Read the discussions before treating silence as approval.

Also in these discussions

No other repository is repeatedly linked in the same discussions.

This week on Hacker News

Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 3:56:07 PM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by year12 dated mentions

Observed mentions: 2020-06-29 19:42:16 UTC to 2026-06-03 02:47:33 UTC.

02462020-01-01 00:00:00 UTC to 2021-01-01 00:00:00 UTC (exclusive): 1 mentions; 1 submissions, 0 comments20202021-01-01 00:00:00 UTC to 2022-01-01 00:00:00 UTC (exclusive): 6 mentions; 2 submissions, 4 comments2022-01-01 00:00:00 UTC to 2023-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2023-01-01 00:00:00 UTC to 2024-01-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 comments20232024-01-01 00:00:00 UTC to 2025-01-01 00:00:00 UTC (exclusive): 3 mentions; 0 submissions, 3 comments2025-01-01 00:00:00 UTC to 2026-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2026-01-01 00:00:00 UTC to 2027-01-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 comments. Incomplete calendar period.2026*

* An incomplete calendar period is marked with an outlined bar. Its count is not directly comparable with a full period.

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

View mention counts and date ranges
UTC ranges include their start and exclude their end. Select a period to filter the source evidence.
PeriodStart (UTC)End (exclusive, UTC)MentionsSubmissionsComments
20202020-01-01 00:00:00 UTC2021-01-01 00:00:00 UTC110
20212021-01-01 00:00:00 UTC2022-01-01 00:00:00 UTC624
20222022-01-01 00:00:00 UTC2023-01-01 00:00:00 UTC000
20232023-01-01 00:00:00 UTC2024-01-01 00:00:00 UTC101
20242024-01-01 00:00:00 UTC2025-01-01 00:00:00 UTC303
20252025-01-01 00:00:00 UTC2026-01-01 00:00:00 UTC000
2026 (partial)2026-01-01 00:00:00 UTC2027-01-01 00:00:00 UTC101

What Hacker News says

12 sources
Well, using something related/similar to turing-complete correspondence: ---- If it can fetch/display files from the internet, yes, it can run doom[5]. Or make use of curl, curl-doom[18] ----- stripped down doom can run in 4MB (doom on a smart toothbrush[7]). ESP32 has support for up to 4MB external PSRAM[1]. ESP32 port of doom[2]. lcd screen might provide for faster refresh / less blury images under magnifying glass. Alternatively, adding an expansion port to be able to use 'doomchip' might make it easier hide game play while at work[8] / stay awake between screen frame refreshes. (and/or simulateously play tetris & 1d pacman; add Badgey functionality[19] ) But should one go with micropython[3], reflectionsOS[4] or not waste space and use a 2 stage 512k bootloader for dns.doom[5]? contikiOS[6] for dns.doom[5] might be the correct fit wi
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thout needing to add 4mb psram / doomchip expansion port(s). ----- Misc doomchip information: doomchip non-tech article(2020)[11]. doomchip developer comments[12]. Should be able to get at least 2fps! doomchip better expanded upon in a 'heads up, 7up' thread -> slice[9]/doomchip[10]. ---- Surprised there's no dns doom.wad / I.D.Software Application (IDSA) rfc "Spit.wad: A DNS string encoding using Unicode for doom.wad graphics" version of rfc3492: "Punycode: A bootstring encoding of Unicode for Internationalizaed Domain Names in Appliations" (IDNA) [13] (IDSA) rfc might permit formally unifying things like unicode-line-stacker[14], stacked diacretics generator[15], unicodeart[16] and "awesome symbols and characters in a bash prompt"[17]. ------------------------------------------------------------- [0] : "Can it run doom?" : https://canitrundoom.org/ [1] : https://docs.espressif.com/projects/esp-idf/en/latest/esp32/... [2] : https://www.techeblog.com/doom-electronic-badge-emfcamp/ [3] : https://github.com/NoosaHydro/2.4inch_ESP32-2432S024/tree/ma... https://github.com/wojciech-graj/cydoomgeneric [4] : https://github.com/frankcohen/ReflectionsOS [5] : https://undercodetesting.com/dns-can-run-doom-how-2000-dns-r... [6] : https://contiki-os.org/ esp32 https://github.com/contiki-ng/contiki-ng/discussions/3022 [7] : doom on a smarth toothbrush : https://www.youtube.com/watch?v=cO-Are8053g [8] : https://hackaday.com/2020/05/13/the-doom-chip/ [9] : https://github.com/sylefeb/Silice [10] : https://github.com/sylefeb/Silice/blob/master/projects/READM... [11] : doomchip article : https://www.techeblog.com/doom-chip-game/ [12] : https://threadreaderapp.com/thread/1258808333265514497.html [13] : https://www.rfc-editor.org/info/rfc3492/ [14] : https://github.com/axesilo/unicode-line-stacker [15] : https://codepen.io/lingyloll/pen/ooMaYO [16] : https://www.unicodeart.com/gallery/ [17] : https://unix.stackexchange.com/questions/25903/awesome-symbo... [18] : https://codeberg.org/xsawyerx/curl-doom [19] : https://memory-alpha.fandom.com/wiki/Badgey
In Muxcard, a DIY credit card size computer
> Is the device hackable? AFAIK not at this moment. The firmware is minimal. It is a relatively new device It is just a package around an inexpensive FPGA chip. Published and un-published attacks against it exist. For these reasons the TKey developers call out "[a]ll physical and electrical attacks applied to the board [are out of scope]" in the threat model. https://hackaday.com/2018/09/27/three-part-deep-dive-explain... https://github.com/sylefeb/Silice/blob/draft/projects/ice40-... > There are protections against opening it up. I'd love to see photos if yours is any different than what is on the website.
In A simple, (as-of-yet unidentified) asymmetric Authenticated Key Exchange
Lookup tables are great to produce impressive graphics effects under strict compute limits. I use them in many FPGA projects. On FPGA there is a balance between limited memory (often BRAM) and limited compute, but they can be used to great effect: Tunnel effect (exactly as user bemmu described below): - see it live: https://htmlpreview.github.io/?https://github.com/sylefeb/gf... - lookup table: https://github.com/sylefeb/gfxcat/blob/main/tunnel/tunnel.h - how it is computed: https://github.com/sylefeb/Silice/blob/master/projects/ice-v... Julia fractal, with a table to do integer multiply! (2.a.b = (a+b)^2 - a^2 - b^2, so just precompute all x^2 in a table! ) - see it live: https://htmlpreview.github.io/?https://github.com/sylefeb/gf... - code (see 'sq' table): https://github.com/sylefeb/gfxcat/blob/main/julia/julia.c - credits (mul tri
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ck): http://cowlark.com/2018-05-26-bogomandel/index.html In-hardware lookup division for perspective correct texturing! - doom-chip on-ice (rC3 2021 talk): https://www.youtube.com/watch?v=2ZAIIDXoBis - detailed write up: https://github.com/sylefeb/tinygpus?tab=readme-ov-file#preco... - actual lookup table generation: https://github.com/sylefeb/tinygpus/blob/498be1b803d0950328a... Sine tables are also very typical, for animating things on screen or plain trigonometry, for instance my small fixed integer raytracer uses a sine table to animate the spheres (and the cos is easy to get from the sin, especially if the table has a power of two size ;) ): - see it live: https://htmlpreview.github.io/?https://github.com/sylefeb/gf... - source code: https://github.com/sylefeb/gfxcat/blob/main/raytrace/raytrac... And of course procedural textures!! Perlin noise is made of lookup tables, and often multiple lookups are combined to then lookup a clolormap (https://redirect.cs.umbc.edu/~ebert/691/Au00/Notes/procedura...) There are so many other examples. Also, FPGAs are quite literally made of LookUp Tables, or LUTs: - https://github.com/sylefeb/Silice/tree/master/learn-silice#f... - https://github.com/sylefeb/silixel (edit: formatting)
In How video games use lookup tables
Hi, Silice author here. I picked the AGPL 3.0 knowing it is on the strict side of the spectrum, but not thinking it would be 'toxic'? If you have some pointers on this I'd like to learn more. In particular, I'd like Silice to be under a GPL style license (so that everyone benefits from improvements), but also to ensure that what is produced with Silice (designs coming in/out of it) is not 'contaminated' by the license. There's a related issue in Silice github on this: https://github.com/sylefeb/Silice/issues/106
In The Ice-V: a simple, compact RISC-V RV32I implementation in Silice
Hi, Silice author here. I cannot provide a detailed answer as I am not familiar enough with SystemC. I started Silice as a "quality of life" (in the video game sense) thin layer above Verilog, hoping to obtain something that would be more enjoyable to write with. I'd like this to be true both for getting started with FPGA, but also when describing advanced designs with efficiency concerns in mind (LUT count, max perf, hardware specificity such as DSP blocks, etc.). In many ways Silice is very simple. Just a thin abstraction layer with helpful syntax helpers (groups, interfaces, pipelines, fsm), automating some checks and performing simple optimizations (e.g. flip-flop pruning). But please see the README for all details. The spirit in which I am developing Silice is "I hope you'll find it useful" and absolutely not "this will be the defini
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tive HDL". First, I am surely not qualified enough to imagine achieving such a goal, and second I am a big believer in having various tools for various problems and various styles. So I hope you'll find it useful :) I am taking great care in providing a build system to make it easy to get started both in simulation and real FPGA hardware. This relies on many other great projects: yosys, nextpnr, edalize, openfpgaloader, verilator, icarus, ... Also, Silice comes with fun examples! https://github.com/sylefeb/Silice/tree/master/projects
In The Ice-V: a simple, compact RISC-V RV32I implementation in Silice

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