Silice

Hi, Silice author here -- about the license see also discussion here https://news.ycombinator.com/item?id=27575174 and github issue https://github.com/sylefeb/Silice/issues/106

Hi, Silice author here. I picked the AGPL 3.0 knowing it is on the strict side of the spectrum, but not thinking it would be 'toxic'? If you have some pointers on this I'd like to learn more. In particular, I'd like Silice to be under a GPL style license (so that everyone benefits from improvements), but also to ensure that what is produced with Silice (designs coming in/out of it) is not 'contaminated' by the license. There's a related issue in Silice github on this: https://github.com/sylefeb/Silice/issues/106

Hi, Silice author here. I cannot provide a detailed answer as I am not familiar enough with SystemC. I started Silice as a "quality of life" (in the video game sense) thin layer above Verilog, hoping to obtain something that would be more enjoyable to write with. I'd like this to be true both for getting started with FPGA, but also when describing advanced designs with efficiency concerns in mind (LUT count, max perf, hardware specificity such as DSP blocks, etc.). In many ways Silice is very simple. Just a thin abstraction layer with helpful syntax helpers (groups, interfaces, pipelines, fsm), automating some checks and performing simple optimizations (e.g. flip-flop pruning). But please see the README for all details. The spirit in which I am developing Silice is "I hope you'll find it useful" and absolutely not "this will be the defini

I was more interested in the Silice project above: https://github.com/sylefeb/Silice/tree/draft