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tenstorrent
riscv-ocelot
SystemVerilog2023–2026
tenstorrent / riscv-ocelot

riscv-ocelot

Ocelot: The Berkeley Out-of-Order Machine With V-EXT support

3Distinct people
4Mentions
0Explicit recommenders
4GitHub stars
REPOSITORY AT A GLANCE

What to know before exploring

What it is

Ocelot: The Berkeley Out-of-Order Machine With V-EXT support

GitHub

Where it is used

No documented product use has been verified yet.

What people are saying

No recommendation phrase was found in the indexed comments.

No classified warning is attached to this page. Read the discussions before treating silence as approval.

Also in these discussions

No other repository is repeatedly linked in the same discussions.

This week on Hacker News

Nov 7–Nov 14 UTC · Direct repository links and separately labeled related project stories. Indexed through 11/14/2026, 5:04:57 PM UTC.

No direct repository links were found in the indexed HN discussions over the past seven days. Older discussions are available below.

Mentions over time

HN mentions by year4 dated mentions

Observed mentions: 2023-03-26 11:37:10 UTC to 2026-03-13 17:26:50 UTC.

0122023-01-01 00:00:00 UTC to 2024-01-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 comments20232024-01-01 00:00:00 UTC to 2025-01-01 00:00:00 UTC (exclusive): 1 mentions; 0 submissions, 1 comments20242025-01-01 00:00:00 UTC to 2026-01-01 00:00:00 UTC (exclusive): 0 mentions; 0 submissions, 0 comments2026-01-01 00:00:00 UTC to 2027-01-01 00:00:00 UTC (exclusive): 2 mentions; 0 submissions, 2 comments. Incomplete calendar period.2026*

* An incomplete calendar period is marked with an outlined bar. Its count is not directly comparable with a full period.

Counts come from the repository’s dated source evidence. Index cutoff: 2026-11-02 08:16:59 UTC.

View mention counts and date ranges
UTC ranges include their start and exclude their end. Select a period to filter the source evidence.
PeriodStart (UTC)End (exclusive, UTC)MentionsSubmissionsComments
20232023-01-01 00:00:00 UTC2024-01-01 00:00:00 UTC101
20242024-01-01 00:00:00 UTC2025-01-01 00:00:00 UTC101
20252025-01-01 00:00:00 UTC2026-01-01 00:00:00 UTC000
2026 (partial)2026-01-01 00:00:00 UTC2027-01-01 00:00:00 UTC202

What Hacker News says

4 sources
> anybody can’t build a RISC-V chip Yes, they can. My point is that nobody needs to give you permission. You can pretend that does not matter but China is about to educate us about what this means rather dramatically in the next few years. And India is building RISC-V chips. And Europe is building RISC-V chips. Tenstorrent started in Canada (building RISC-V chips). > the number who can get or own a FAB to manufacture the chips Really? Almost nobody owns fabs and yet there are a multitude of chip makers. Getting access to a fab requires only money. It has nothing to do with the ISA or your skills. TSMC can make RISC-V chips just fine and already do. In some places, like China, RISC-V chips may be at the front of the line. > The number of people who can design a chip implementation of the RISC-V ISA Anybody can build a RISC-V chip. Build on
Read the rest
e yourself: https://github.com/tscheipel/HaDes-V Every electrical engineer is going to know how to design a RISC-V chip. But you could also be an intelligent garbage man and design a RISC-V chip in your spare time using only open source materials. You can even tape it out. https://tinytapeout.com/ "But that is only a 32 bit microcontroller!", you might say. Sure. But the skills to build RISC-V are going to propogate. Of course, that does not mean that everybody in the world is going to figure out how to build chips. That is clearly not my point. They will still be built primarily by a select few. But that is not unique to RISC-V by any stretch. In fact, less so. The hard part about building a chip from scratch is not the ISA. You think that a world-class engineer working with ARM64 or amd64 today cannot design a RISC-V chip? That is like saying a carpenter building oak cabinets lacks the skills to make them with maple. And since it is the same amount of work to start fresh regardless of ISA, why not start with RISC-V? Except you do not have to start fresh with RISC-V because there are many, and will be many, many more, open designs to study and start with. Here is a 64 bit chip that implements the very latest RISC-V vector extensions: https://github.com/tenstorrent/riscv-ocelot Which, by the way, means that although most won't, anybody can build a RISC-V chip. The RISC-V world will look like ARM. Most chip makers will license the core design off somebody else. But there will be more of those "somebody elses" to choose from. And there will be more people who choose to design their own silicon. Meta just bought Rivos. What for do you think? And they did not have to talk to ARM about it.
In RISC-V Is Sloooow
That price is very good - even better is the fact that you can actually buy these right now (ships in 2 weeks apparently) by going to their website! So many AI startups are PoA, only B2B etc. I did some 5 second digging into their code and it seems based on their Github that they took Berkeley's BOOM CPU (written in Chisel), and added support for the Vector 1.0 extension, and then they've called this core Ocelot. Seems like the core is open source at least. https://github.com/tenstorrent/riscv-ocelot/blob/bobcat/READ... Not sure about the driver/software situation though. Do you actually get to run whatever RISC-V code you want on these? Could be amazing if so.
In Tenstorrent Unveils High-End Wormhole AI Processors, Featuring RISC-V

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