chipyard

I learned recently that one of the killer apps for Scala seems to be in hardware design. Chisel [0] is the core technology of the best open source RISC-V chips. Chipyard [1] is designing leading edge type OOE and AI chips and all of the code is written in Scala. Personally, I can't wait for some of these designs to start being mass produced and put in laptops and phones. [0] https://en.wikipedia.org/wiki/Chisel_(programming_language) [1] https://github.com/ucb-bar/chipyard

I think Chisel's main win is that it is great from an open-source research perspective. Taking advantage of the functional nature of Chisel enables a set of generators called Chipyard [0] for things like cores, networking peripherals, neural network accelerators, etc. If you're focusing on exploring the design space of one particular accelerator and don't care too much about the rest of the chip, you can easily get a customized version of the RTL for the rest of your chip. Chisel handles connecting up all the components of the chip. All the research projects in the lab benefit from code changes to the generators. Chisel even enables undergraduate students (like me!) to tape out a chip on a modern-ish process node in just a semester, letting Chisel significantly reduce the RTL we have to write. Most of the remaining time is spent working o

Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out. If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardw

I think in general Chisel has more people working on it. However, most people using Chisel are targeting ASICs, thus Spinal HDL wins when it comes to supporting features that are important to FPGAs. Chisel also hasn't anything close to the awesome VexRiscV core which was developed for FPGAs. The most developed cores written in Chisel are much bigger and more complex as they target ASICs. See the chipyard repository which tries to lower the learning curve a little bit : https://github.com/ucb-bar/chipyard/