riscv-sodor

Is there any published rationale for the RISC-V instruction encoding? A few months back I set out to write a software emulator of RISC-V for fun. I expected the instruction set encoding to lend itself well to a very simple implementation, eg. something you could decode in 5-10 lines of C plus some tables. But the instruction encoding is much more irregular than I expected: https://github.com/ucb-bar/riscv-sodor/blob/master/src/commo... In particular: - The bit patterns allocated to the simplest instructions (eg. rv32i) seem random. Why not allocate starting from zero to allow dense jump tables? - I can't make any sense of the groupings. A bunch of instructions have 0b1100011 in the lowest bits, do these instructions have something in common? I assume there is some rhyme and reason to all this? Where is th

The error is understandable, the main prototype RISC-V core is written in Chisel and the "Rocket Core Generator" is written in Chisel. The RISC-V team at Berkeley has a lot of overlap with the Chisel team. So it is easy to think RISC-V is all Chisel. I believe Chisel, Chisel, RISC-V, Chisel, if that makes any sense. https://riscv.org/wp-content/uploads/2015/01/riscv-rocket-ch... https://github.com/freechipsproject/rocket-chip (parametric SoC generator, Chisel) https://github.com/ucb-bar/riscv-sodor (Chisel) https://chisel.eecs.berkeley.edu/

It's great to see how RISC-V has stimulated a lot of activity in open source CPU design. There are a few implementations now: * Rocket https://github.com/ucb-bar/rocket-chip * lowRISC ASIC http://www.lowrisc.org/ * PicoRV32 https://github.com/cliffordwolf/picorv32 * BOOM (derived from Rocket) https://github.com/ucb-bar/riscv-boom * SODOR https://github.com/ucb-bar/riscv-sodor * VSCALE https://github.com/ucb-bar/vscale Anyone know of any more?

Definitely, if you just want implement one in a HDL. For instance the RISC-V ISA has been implemented multiple times in various languages [for instance: https://github.com/ucb-bar/riscv-sodor]. RISC-V is quite a bit more complex than the 4004 ISA. If you want to DIY the entire chip, as in manually lay out the transistors, I suppose it can be done if you have quite a bit of experience in electrical engineering, but it'd be rather cumbersome given the 'modern' (as far as HDL tooling is modern) tooling that is already available.

It's actually really pretty easy to do. I put together a handful of different RISC-V cores that all implement the privileged/supervisor spec (https://github.com/ucb-bar/riscv-sodor/blob/master/src/rv32_...). Basically, detect a few cases in Decode, pass the rest of the instruction down the pipeline to the commit(memory) stage, and let the commit stage detect exceptions and redirect the PC as required.

You're asking for a picture of a particular RISC-V implementation and its chosen microarchitecture. The RISC-V ISA has a range of different implementations each hitting different points in the design space and different trade-offs in terms of area/performance. See for instance the 'Sodor' teaching cores https://github.com/ucb-bar/riscv-sodor https://github.com/ucb-bar/riscv-sodor/wiki which demonstrate 1-stage, 2-stage, 3-stage, 5-stage, and micro-coded implementations.