swerv_eh1

For values of "now" equal to 2019 https://github.com/westerndigitalcorporation/swerv_eh1

Western Digital announced an open source core ("SweRV") in 2019, so I assume they already use them now that we are a few years on from that announcement. https://github.com/westerndigitalcorporation/swerv_eh1 https://news.ycombinator.com/item?id=25002448

It's confusing that RISC-V is so often described as "open source". The specs (ISA + extensions) are open and free from patents (at least as far as we know). While there are a large number of open source implementations available, many of these, however, implement only a simple microcontroller-style RV32I core. The cores available in "large" physical chips you can buy today (XuanTie C906 on the Allwinner D1 SoC, SiFive U54/74 e.g. on the BeagleV and HiFive Unmatched) are proprietary. I think one of the few companies that open sourced their commercially used cores is Western Digital ("swerv" cores - https://github.com/westerndigitalcorporation/swerv_eh1), but these are also RV32I microcontroller-class CPUs.

WD is a very active contributor to RISC-V, some of their "SweRV" RISC-V cores are open source: https://github.com/westerndigitalcorporation/swerv_eh1

There is a lot of open hardware, also a lot published by private companies. See e.g. https://ohwr.org/, https://opencores.org/ or https://github.com/westerndigitalcorporation/swerv_eh1_fpga https://github.com/westerndigitalcorporation/swerv_eh1

https://github.com/antonblanchard/microwatt Although I guess it is less relevant now Western Digital has open sourced their RISC-V design as well. https://github.com/westerndigitalcorporation/swerv_eh1

You can, verilator https://www.veripool.org/wiki/verilator is a free and very performant way of doing so. It's not that hard to get into. SwerV https://github.com/westerndigitalcorporation/swerv_eh1 uses it and Chisel uses it as a backend.

There is so much to unpack in this article. I pick this claim: That RISC-V is a simple(r) architecture and therefore meaningfully easier to verify[0]. The base RISC-V ISA is indeed very small. However, to compete with ARM/MIPS/x86 usefully as an application core, one must include many standard extensions. All of which add comparable complexity to the ARM/MIPS feature which they ape. It feels wrong to assert then without some serious qualification that RISC-V is simpler or easier to verify. A RISC-V core is no more or less complex to verify than a comparably featured ARM/MIPS core. That said, and open ISA like RISC-V can really lead the way in terms of shared verification IP. That is the benefit to an open ISA, not it's simplicity, but the fact that it becomes worthwhile for people to share their verification infrastructure. Unfortunately

Can someone explain a bit what’s happening around the division? https://github.com/westerndigitalcorporation/swerv_eh1/blob/... Or give me some google keywords? Is there a link with the pentium bug?